Senior Serdes System Design Engineer/Architect

Job Title

Senior Serdes System Design Engineer/Architect

Role Summary

System/DSP design engineer responsible for architecture, modeling, simulation, and validation of high-speed SerDes physical-layer signal-processing for 100G+ wireline products. Work on system-level algorithms, implement bit-exact models, and partner with analog, digital, and lab teams to deliver production silicon.

Contribute to standards development and provide technical support and documentation for customers and internal teams.

Experience Level

Senior-level. Typical experience expectation: M.S.E.E. +10 years or B.S.E.E. +12 years (per employer requirements).

Responsibilities

Primary responsibilities include system architecture, modeling, verification, and lab validation of SerDes physical-layer functions.

• Develop channel models and run simulations to define SerDes architecture and tradeoffs.
• Define and document signal-processing block requirements, architecture, and lab test plans.
• Develop bit-exact MATLAB and C/C++ system models for simulation and verification.
• Create and execute system-level simulation suites to evaluate architectural options.
• Perform vector matching verification with RTL simulations and coordinate with design teams.
• Develop, test, and debug firmware related to physical-layer functionality.
• Perform lab testing and hardware debug of SerDes; support DVT and production validation.
• Produce documentation, application notes, and provide customer-facing technical support.
• Support marketing and customer meetings with technical collateral.

Requirements

Must-have technical skills and experience:

• Expert knowledge of communication theory and digital signal processing algorithms.
• Proven experience implementing bit-exact system models in MATLAB and C/C++.
• Working knowledge of analog circuit behavior and hands-on lab debugging skills.
• Working knowledge of transmission line theory and S-parameters.
• Experience with system-level simulation, verification, and coordinating RTL interactions.
• Ability to develop and debug firmware associated with physical-layer features.

Nice-to-have:

• Experience designing high-speed CDRs/PLLs.
• Experience with equalization techniques for wireline/read-channel applications.
• RTL coding experience.
• Familiarity with IEEE 802.3, OIF 100G/200G/400G, and PCIe Gen6/Gen7 standards.

Education Requirements

Required: B.S. in Electrical Engineering with ~12+ years relevant experience, or M.S. in Electrical Engineering with ~10+ years relevant experience (per employer posting). Fields referenced: Electrical Engineering or closely related technical disciplines. No certifications explicitly required.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.