Senior SERDES/C2C First-Silicon Bring-Up Engineer

Job Title

Senior SERDES/C2C First-Silicon Bring-Up Engineer

Role Summary

Responsible for converting verification and simulation sequences into a deterministic, diagnosable physical bring-up flow for SERDES and chip-to-chip (C2C) links. The engineer will isolate and resolve failures across PHY/modem, clocking/calibration, and digital controller layers and collaborate across hardware, firmware and verification teams.

Position is based in Barcelona with a hybrid schedule: four days per week in the city-center office and one day remote.

Experience Level

Senior. Prior hands-on first-silicon SERDES or high-speed PHY bring-up experience is required.

Responsibilities

Key responsibilities during bring-up and early silicon debug include:

• Review and reconcile verification/simulation sequences with physical bring-up requirements.
• Define and establish ordering for reference-clock, reset, physical-modem, calibration, controller and link-training steps.
• Implement or review low-level C/C++ register sequences, MMIO, and status polling.
• Define bounded timeout, readback and failure-classification behavior for deterministic flows.
• Execute and debug physical link bring-up together with internal technical owners.
• Use link status, retry/error counters and real data transactions to distinguish PHY readiness from functional-link readiness.
• Produce repeatable logs, register snapshots and failure evidence suitable for regression and traceability.

Requirements

Must-have technical skills and experience:

• Hands-on first-silicon SERDES or high-speed PHY bring-up experience.
• Strong understanding of PLL, CDR, reference-clock selection, reset sequencing, calibration and lane readiness.
• Experience with TX/RX configuration, termination, equalization, polarity/lane configuration and link-training flows.
• Ability to debug links that do not reach expected operational state using status registers, counters and physical measurements.
• Low-level C/C++ firmware development experience, MMIO/register programming and bounded polling/error handling.
• Ability to correlate RTL/UVM/cosimulation collateral with physical silicon behavior without assuming simulation conditions match silicon.
• Practical use of oscilloscopes and high-speed/debug laboratory equipment.
• Experience working across hardware, firmware and verification teams during first-silicon debug.

Preferred:

• Chip-to-chip, chiplet or die-to-die (C2C) interface experience.
• Experience with Cadence SERDES/PHY IP or comparable commercial PHY IP.
• Experience with PHY firmware, embedded PHY microcontrollers, calibration firmware or mailbox/control interfaces.
• Experience building deterministic bring-up gates and reusable evidence rather than ad-hoc lab procedures.

Education Requirements

Not specified.

About the Company

Company: Semidynamics

Headquarters: Barcelona, Spain

Semidynamics is a company specializing in infrastructure verification and automation solutions. They focus on optimizing resources and enhancing continuous integration processes in design verification. The team collaborates to maintain regression test infrastructure and develop efficient workflows.