Senior RTL Engineer, IO Die and Interconnect IP

Job Title

Senior RTL Engineer, IO Die and Interconnect IP

Role Summary

Join the AGI Computing Lab to design RTL and microarchitecture for IO die subsystems in chiplet-based architectures. The role focuses on integrating and customizing high-speed interconnect IP (UCIe, PCIe, CXL, die-to-die, NoC) and delivering die-level integration across performance, power, and interoperability constraints.

Work closely with architecture, PHY/SerDes, physical design, verification, and software teams at the San Jose, CA office to implement, validate, and deliver IO subsystems for advanced AI/ML platforms.

Experience Level

Senior — typical experience guidance: Bachelor's +5 years, Master's +3 years, or PhD +0 years of relevant industry experience.

Responsibilities

Primary responsibilities include RTL design, IP integration, and system-level collaboration to deliver IO die functionality.

• Develop RTL (Verilog/SystemVerilog) for IO die components and subsystems.
• Integrate internal and third-party interconnect IP (UCIe, PCIe, CXL, die-to-die, NoC) including configuration, glue logic, clock/reset, and interface bridging.
• Customize or modify third-party IP (controllers, PIPE/PHY interfaces, configuration logic) to meet die-level requirements.
• Define and implement die-to-die and chiplet interfaces to ensure protocol compliance and interoperability.
• Own microarchitecture and RTL for IO subsystems such as PCIe/CXL controllers, UCIe adapters, and interconnect fabric bridges.
• Collaborate with verification to develop test plans and debug issues at IP, subsystem, and die levels.
• Work with architecture, PHY/SerDes, physical design, and software teams to meet performance, power, area, and interoperability targets.
• Make trade-off decisions across performance, power, latency, bandwidth, and cost.
• Develop and automate IP integration and RTL assembly flows using scripting and automation tools; leverage agentic AI tools where appropriate.
• Communicate status and technical decisions to stakeholders and help ensure on-time die delivery.

Requirements

Must-have technical skills and experience; preferred items noted where applicable.

• Strong microarchitecture and RTL design experience for complex SoC and die integration.
• 5+ years of RTL development (Verilog/SystemVerilog) for high-speed interconnect and IO subsystems.
• Hands-on experience integrating and configuring interconnect IP such as PCIe, CXL, UCIe, and die-to-die interfaces.
• Experience modifying or customizing third-party interconnect IP (controller, PIPE/PHY interface) to meet die requirements.
• Solid understanding of PCIe/CXL protocol stacks (transaction, data link, physical layers) and the PIPE interface.
• Familiarity with chiplet-based, multi-die architectures and UCIe-based die-to-die interfaces.
• Experience with SoC integration methodologies and on-chip interface protocols (AXI, ACE, CHI, APB); familiarity with IP packaging (e.g., IP-XACT).
• Proficiency in scripting (Tcl, Python, or Perl) for design integration and automation; experience with automation or AI-assisted tooling is a plus.
• Experience with AI/ML workloads or platforms is a plus.
• Strong analytical, problem-solving, communication, and collaboration skills; ability to work independently and in cross-functional teams.

Education Requirements

Degree options with equivalent experience: Bachelor's degree with 5+ years of relevant industry experience, Master’s degree with 3+ years, or PhD with 0+ years. Equivalent practical industry experience will be considered.

About the Company

Company: Samsung Semiconductor

Headquarters: San Diego, California, United States

Samsung Semiconductor is a global leader in semiconductor technology, providing innovative solutions for diverse applications including smartphones, electric vehicles, and data centers. As part of Samsung's Advanced Institute of Technology, the company focuses on cutting-edge research in areas such as CPU microarchitecture, AI, and HPC, fostering a diverse and inclusive work environment for its employees to thrive and innovate.