Job Title
Senior RTL Digital Design Engineer – ASIC/VLSI
Role Summary
The Senior RTL Digital Design Engineer will develop RTL for next-generation DSP solutions within an ASIC/VLSI environment. The role focuses on implementing architecture into synthesizable RTL, collaborating with verification and physical design teams, and supporting integration toward tapeout.
Experience Level
Senior — minimum 5 years of relevant experience in RTL/ASIC or VLSI digital design.
Responsibilities
Primary responsibilities include:
- Design and implement synthesizable RTL for DSP and ASIC modules.
- Collaborate with verification, physical design, and system teams to meet functional, timing, and integration goals.
- Participate in architecture and design reviews and provide technical guidance on implementation choices.
- Optimize designs for area, power, and performance; support bring-up and silicon validation activities.
- Produce and maintain design documentation and mentor junior engineers.
Requirements
Must-have:
- At least 5 years of experience in digital/RTL design for ASIC or VLSI projects.
- Strong RTL coding skills.
- Experience working collaboratively in fast-paced engineering teams.
- Experience in semiconductor or DSP-related projects.
Nice-to-have: Information not specified.
Education Requirements
Not specified.
About the Company
Company: NewsNowGh
NewsNowGh appears to be a news/job aggregator that reposted this listing. The actual hiring employer (an Austin, Texas-based semiconductor/tech company) is not identified in the posting.

Date Posted: 2026-05-21