Senior RTL Design Manager

Role Overview

We seek an experienced RTL Design Manager to lead a high-performance design team responsible for the delivery of industry-leading DDR IP solutions. The successful candidate will possess a robust technical background in digital logic design and RTL development flows while demonstrating leadership in mentoring a talented team of engineers.

Experience Level

The ideal candidate should have a minimum of 15 years of experience in digital logic design, including at least 2 years in people management and employee development.

Key Responsibilities

The role entails:

• Providing technical leadership and delivering high-quality DDR IP solutions that exceed benchmarks for speed, bandwidth, efficiency, latency, and power.
• Collaborating with architecture and verification teams to drive the RTL design process from micro-architecture definition to production.
• Overseeing the integration of IP blocks into SoCs and ensuring design adherence to performance, power, functionality, and quality standards.
• Leading, mentoring, and developing a team of RTL design engineers while fostering a culture of technical excellence and continuous improvement.
• Establishing robust design methodologies and best practices for high-quality RTL delivery.

Requirements

The candidate must have:

• Proficiency in Verilog / System Verilog and synthesizable design concepts.
• Sound understanding of front-end design flows and EDA tools including static timing analysis and DFT.
• Experience in digital logic verification and UVM, as well as scripting abilities in Perl, Python, or TCL.
• Knowledge of advanced process nodes (5nm, 7nm) and familiarity with DDR or LPDDR.
• Excellent communication and analytical skills to resolve complex problems.

Education Requirements

A Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is required.