Senior RTL Design Engineer

Job Title

Senior RTL Design Engineer

Role Summary

Hands-on individual contributor responsible for designing, integrating, and bringing RTL to sign-off for blocks in an ultra-low-power SoC: on-chip interconnect/NoC, memory interfaces, low-power/AON logic, and standard peripherals (RISC-V, NVM, I2S, I2C).

You will take blocks from microarchitecture specification through synthesis-ready RTL, working with architecture, DV, physical design, and firmware to support tapeout and silicon bring-up.

Experience Level

Senior - typically 8–10+ years of front-end digital design experience on processor, accelerator, or SoC products; significant contribution to multiple tapeout cycles.

Responsibilities

Deliver RTL and integrate IP across subsystem and SoC levels while ensuring front-end quality, timing, and low-power correctness.

• Implement microarchitecture and synthesizable SystemVerilog RTL for assigned blocks (NoC, memory interfaces, peripherals, datapath and control logic).
• Integrate third-party and in-house IP (RISC-V cores, NVM controllers, SRAM wrappers, APB/I2C/I2S peripherals) and memory-mapped register interfaces.
• Maintain and present uArch/design documentation in reviews with architecture, DV, and physical design.
• Own front-end sign-off tasks: lint-clean RTL, CDC/RDC analysis and waivers, LEC against netlist.
• Run synthesis, write/maintain SDC constraints, analyze STA reports, and iterate RTL to meet timing, area, and power targets.
• Implement UPF-driven low-power RTL: power domains, isolation, level shifters, retention, and clock gating.
• Support verification and bring-up: block-level and gate-level simulation, debug with waveform tools, and assist silicon lab validation.
• Drive closure with physical design on timing, congestion, and power issues.

Requirements

Key qualifications and skills required and preferred for the role.

Must-have:

• 8–10 years front-end digital design experience on processors, accelerators, or SoCs with contributions to multiple tapeouts.
• Strong SystemVerilog skills for synthesizable RTL (state machines, arbiters, FIFOs, flow control, datapath).
• Practical experience with front-end flows: lint, CDC/RDC, LEC, synthesis, SDC constraints, and STA; ability to interpret reports and act.
• Experience with low-power RTL techniques and UPF-driven flows: clock gating, power domains, isolation, and retention.
• Working knowledge of at least one on-chip bus protocol at the RTL level (AXI, AHB, APB, TileLink, or equivalent).
• Experience with on-chip memories: SRAM wrappers, banking, and memory-mapped registers.
• Comfortable running RTL and gate-level simulations and debugging with waveform tools.
• Clear written and verbal communication; able to document designs and present in reviews.

Nice-to-have:

• Experience designing or integrating on-chip networks, dataflow pipelines, or memory subsystems.
• Familiarity with NVM controller RTL (MRAM, RRAM), ECC, and sequencing.
• Experience with RTL/gate-level power analysis tools and methodologies.
• Understanding of parallel execution models (dataflow, SIMD, systolic arrays).
• Exposure to DFT concepts: scan insertion, ATPG, and DFT-friendly RTL coding.
• Scripting skills for flow automation (Python, Tcl, Perl).

Education Requirements

Not specified.

About the Company

Company: Efficient Computer

Headquarters: Austin, TX, USA

Developer of ultra-low-power general-purpose processors using patented technology that can consume up to 100x less energy than comparable ultra-low-power processors. Their programmable platform supports standard high-level languages and AI/ML frameworks to enable long-lived, battery-powered edge devices and energy-efficient SoCs for IoT and edge AI applications.