Senior RTL Design Engineer

Job Title

Senior RTL Design Engineer

Role Summary

Design and deliver production-ready RTL for complex digital subsystems, translating architectural specifications into efficient microarchitectures with attention to performance, power, and area. Work closely with architecture, verification, and physical design teams to ensure correctness from RTL through synthesis and integration.

Small, engineering-driven startup building foundational technology for large-scale AI data center clusters.

Experience Level

Senior - typically 5+ years of RTL design experience; role expects deep hands-on experience and ownership of RTL delivery.

Responsibilities

Deliver and integrate RTL and participate across the full design lifecycle.

• Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog.
• Translate architectural specs into clean, efficient, and scalable microarchitectures.
• Develop reusable, well-documented RTL with strong coding standards.
• Perform linting, CDC analysis, and prepare designs for synthesis.
• Support simulation, integration, and debug in simulation and early silicon environments.
• Collaborate with verification and backend teams to achieve functional coverage and timing closure.
• Participate in design reviews and advise on architecture vs. implementation tradeoffs.
• Improve design methodologies, flows, and tooling; support automation and AI-assisted workflows where useful.

Requirements

Must-have technical skills and experience; desired items noted separately.

• 5+ years of practical RTL design experience.
• Strong hands-on experience with Verilog/SystemVerilog.
• Solid understanding of synchronous digital design and microarchitecture principles.
• Experience with simulation and debug tools (e.g., VCS, Questa, Verdi, DVE).
• Familiarity with synthesis, timing constraints, and physical design considerations.
• Strong analytical, problem-solving, and communication skills for cross-functional collaboration.
• High attention to detail and ability to independently deliver high-quality designs.
• Experience integrating AI-assisted tools into RTL workflows and verifying AI-generated outputs.

Nice-to-have:

• Experience with high-performance systems (AI/ML accelerators, networking, SoCs).
• Low-power design techniques (clock gating, power gating) and DFT exposure.
• Scripting skills (Python, Tcl) and experience with advanced process nodes.
• Experience creating reusable AI agent guidance such as coding patterns or timing-closure playbooks.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: Delos Data

Headquarters: Palo Alto, CA, United States

Stealth-mode Silicon Valley startup building foundational technology to improve performance, scalability, and resiliency of large-scale AI data center clusters. Backed by venture capital and led by experienced founders, the company develops hardware/software solutions and operates across U.S. and Canadian locations.