Senior RTL Design Engineer

Role Summary

The Senior RTL Design Engineer role at Synopsys involves developing specifications and RTL for High Bandwidth Interface PHY IP, collaborating with verification teams, and applying scripting skills for design automation. The position is part of a talented engineering team focused on innovative PHY IP solutions.

Experience Level

Mid-level; requires a minimum of 2 years in RTL design for ASIC or PHY IP.

Responsibilities

The key responsibilities include:

• Developing specifications and RTL for High Bandwidth Interface PHY IP.
• Collaborating with Verification teams to ensure design accuracy.
• Coordinating logic implementation phases across teams.
• Applying scripting skills for design automation.
• Participating in onboarding in Da Nang and transitioning to Hanoi or Ho Chi Minh City.

Requirements

Candidates must fulfill the following requirements:

• BS/MS/PhD in Electronics Engineering or Telecommunications.
• 2+ years in RTL design for ASIC or PHY IP.
• Experience with VCS, Verdi, Spyglass, Perl/TCL/Python.
• Knowledge of clock domain crossing, APB, JTAG.
• Good English communication skills.

Education Requirements

Bachelor’s, Master’s, or PhD in Electronics Engineering or Telecommunications.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.