Senior R&D Engineer, Formal Verification
Senior engineer on the Formality R&D team responsible for designing and implementing algorithms and tools for formal verification of chip designs. The role focuses on C++ development, solver techniques, and improving the performance and accuracy of Formality.
The position involves research and engineering activities, collaboration with other engineers, and translating research ideas into production-quality EDA tools.
Senior-level. Years of experience not specified.
Key responsibilities include development, research, and collaboration to improve Formality's capabilities and performance.
Required technical skills and experience for successful performance in this role.
PhD, MS, or ME in Computer Science or Electrical Engineering is specified.
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
