Senior Product, Test and Yield Enhancement Engineer - Taiwan

Job Title

Senior Product, Test and Yield Enhancement Engineer - Taiwan

Role Summary

Senior VLSI product and test engineer responsible for driving test strategy, failure analysis and yield enhancement for wafer-scale AI processors in Taiwan. Works across test development, manufacturing data analysis, wafer disposition and defect characterization in partnership with design and manufacturing teams.

Experience Level

Senior - requires 10+ years of semiconductor product or test-engineering experience.

Responsibilities

Lead and execute production test and yield activities for wafer-scale AI processors and related subsystems.

• Develop and optimize production test programs for wafer-scale AI processors.
• Coordinate high-volume manufacturing testing with foundries and OSAT partners.
• Implement and refine design-for-test strategies (scan, BIST, ATPG, functional test).
• Analyze ATE, Shmoo, parametric and defect data to identify yield and fault-tolerance improvements.
• Develop failure-analysis and fault-isolation methods for defective cores, tiles and functional blocks.
• Design efficient wafer-level test flows for massively parallel compute, mesh/NoC architectures and die-to-die interconnects.
• Collaborate cross-functionally with DFT, architecture, design, performance, software and manufacturing teams.
• Optimize voltage-frequency operating limits, thermal behavior, power delivery and parallel die-testing capabilities.
• Support wafer and lot disposition decisions during high-volume manufacturing.

Requirements

Must-have technical skills and experience for immediate contribution.

• 10+ years of semiconductor product or test-engineering experience supporting highly integrated devices.
• Strong experience in test development, silicon debug, test optimization and yield improvement.
• Experience testing large parallel processors, GPUs, CPUs or networking ASICs incorporating SRAM, DDR/DRAM or HBM.
• Expert-level, hands-on experience with the Advantest V93000 ATE platform; Teradyne experience is a plus.
• Experience specifying, designing and debugging load boards and probe cards for advanced production-test and DFT needs.
• Strong cross-functional collaboration and problem-solving skills.
• Experience working with Git-based development and release flows.

Nice-to-have / preferred:

• Programming experience with C, C++, Python or Perl for large-scale test-data analysis.
• Familiarity with semiconductor test and failure-analysis tools or techniques such as Tessent, OBIRCH, IREM and LADA.
• Experience testing high-speed SerDes at ATE, package or system level.
• Experience with analog blocks embedded in large digital ASICs.
• Experience applying advanced data-analysis or machine-learning techniques to yield optimization.
• Knowledge of wafer-scale packaging, TSVs, advanced interconnects, in-line diagnostics and defect-mitigation techniques.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or a related technical field (as stated in the posting).

About the Company

Company: Cerebras

Headquarters: Sunnyvale, CA, USA

Developer of wafer-scale AI accelerators, Cerebras designs the Wafer Scale Engine (WSE)-one of the world’s largest AI chips-to deliver high-speed training and inference solutions for model labs, enterprises, and AI-native startups.