Senior Product Manager, Hardware (NPU IP)
QuadricJob Title
Senior Product Manager, Hardware (NPU IP)
Role Summary
The Senior Product Manager, Hardware will own the Chimera GPNPU IP roadmap across five strategic tracks: Compute, Efficiency, Scalability, Safety, and Integration. You will set feature sets for upcoming IP generations, drive architecture-freeze decisions, and work directly with anchor SoC customers to ensure the IP ships in production devices.
Experience Level
Senior - typically 5–8 years of product management experience focused on hardware or silicon products with a senior IC background.
Responsibilities
Own technical product decisions and customer integration for the GPNPU IP; coordinate internal architecture, product, and customer teams to deliver production-ready silicon IP.
- Define and prioritize track-by-track feature lists (Compute, Efficiency, Scalability, Safety, Integration) with explicit gating for architecture freeze.
- Build technical and business cases for contested architecture decisions and lead trade-off reviews with architects and the Product Steering Committee.
- Drive IP usability by identifying common customer workarounds and productizing proper architectural solutions.
- Act as named hardware product owner for key anchor accounts and incorporate formal architecture feedback into the roadmap.
- Run architecture reviews with technical buyers, including Tier-1 automotive and OEM SoC design teams.
- Partner with international customers, with emphasis on supporting Japanese and other global semiconductor accounts.
- Monitor competitive architectures and translate competitive intelligence into product requirements and differentiation.
- Specify SoC integration features and which integration knobs (AXI4/ACE-Lite, CoreSight, power domains, performance counters) are exposed and productized.
- Plan functional safety sequencing, lockstep configurations, FMEDA work, and safety-island architectures for automotive/critical applications.
Requirements
Key qualifications and expectations for the role.
Must-have:- 5–8 years of Product Management experience focused on hardware or silicon products, with a senior IC background.
- Direct experience in at least two of: NPU/AI accelerator architecture, SoC integration, DSP/vector compute, automotive silicon, or semiconductor IP licensing.
- Proven track record leading technical architecture reviews with sophisticated buyers (Tier-1 automotive, OEM SoC teams).
- Active adoption of agentic AI tools (e.g., Claude Code, Cursor, or equivalent) in daily workflows.
- Based in or willing to relocate to the Bay Area (Burlingame hybrid model) and able to travel quarterly (domestic and international).
- RTL or silicon implementation background (shipped a block, participated in tape-out, or owned a microarchitecture spec).
- Experience at a semiconductor IP vendor (e.g., Synopsys, Arm, Ceva, Cadence, Imagination, VeriSilicon).
- Direct exposure to AI/ML compute stack architectures (dataflow, quantization, sparsity, mixed-precision trade-offs).
- Experience engaging with Japanese-market customers and technical teams.
Education Requirements
EE/CE/CS engineering degree or equivalent practical depth/experience (the posting states an engineering degree in Electrical Engineering, Computer Engineering, or Computer Science or equivalent depth).
About the Company
Company: Quadric
Headquarters: Burlingame, California, United States
Quadric is building the world’s first supercomputer designed for the real-time needs of edge devices. Founded in 2016, the company empowers developers across industries with innovative general-purpose neural processing unit (GPNPU) architecture for neural network workloads. Co-founded by technologists from MIT and Carnegie Mellon, Quadric aims to enable groundbreaking technology development.
