Senior Principal Verification Engineer

Job Title

Senior Principal Verification Engineer

Role Summary

Lead architecture and execution of mixed-signal verification for automotive PMIC products. Work with design, validation, ATE, and application teams to ensure functional correctness, safety compliance, and silicon readiness.

This role focuses on verification methodology, tool flow development, complex mixed-signal debug, and mentoring verification engineers.

Experience Level

Senior — typically 15+ years of experience in mixed-signal or analog circuit verification, with leadership and mentoring responsibilities.

Responsibilities

Deliver verification strategy, build verification environments, and lead debug and correlation activities for automotive PMIC designs.

• Design and architect mixed-signal verification environments, including Real Number Model (RNM) and AMS model integration for PMICs.
• Develop and implement verification plans and strategies ensuring automotive standards compliance (ISO 26262, AEC-Q200).
• Set up and optimize Gate-Level Simulation (GLS) flows and correlate GLS with RTL results.
• Lead debugging of complex analog blocks (switched-mode regulators, LDOs, bandgaps) and mixed-signal interfaces.
• Run RTL and gate-level simulations; analyze timing, power, and functional correctness across PVT corners.
• Collaborate with Design, Application Engineering, ATE, and Silicon Validation for verification handoffs and test correlation.
• Mentor and lead junior verification engineers; define best practices and verification methodologies.
• Troubleshoot analog–digital interactions using simulation and measurement techniques.
• Drive improvements to verification tools, flows, and infrastructure; evaluate emerging technologies and AI-based solutions.
• Create and maintain verification documentation, test plans, and coverage metrics.

Requirements

Must-have technical skills and professional capabilities for the role.

• 15+ years of experience in mixed-signal or analog circuit verification.
• Deep understanding of mixed-signal verification environment architecture and implementation.
• Hands-on experience with Real Number Model (RNM) and AMS model integration.
• Proficiency with RTL and behavioral simulation tools (example: Spectre, Xcelium).
• Experience setting up and debugging Gate-Level Simulation (GLS) flows.
• Proven ability to debug analog blocks and digital RTL.
• Experience with automotive PMIC or power management IC design and verification.
• Proficiency in Verilog, SystemVerilog, and/or SPICE-based languages.
• Solid knowledge of verification methodologies: UVM, assertions, coverage-driven verification.
• Experience interfacing across verification domains: functional, post-silicon, and ATE test correlation.
• Strong problem-solving, debugging, leadership, and mentoring skills.

Education Requirements

MS or PhD in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.