Senior Principal Software Engineer

Job Title

Senior Principal Software Engineer

Role Summary

Join the Xcelium System Verification Group to architect and enhance the next generation of RTL/logic simulation technology used for complex AI and hyperscale chip designs. Work on simulator engine features, timing-constraints verification, and performance optimization as part of a geographically distributed engineering team.

Experience Level

Senior-level engineer. Typical expectation: 7+ years of software engineering experience; at least 5+ years of experience in EDA or related tooling.

Responsibilities

Hands-on software development and technical leadership in simulator and timing-constraints features.

• Design, implement, and extend features in the Xcelium RTL/logic simulator engine.
• Develop and enhance Timing Constraints Verification and SDC constraints support.
• Design and tune graph algorithms for very large graphs (multi‑billion nodes) related to constraints and timing analysis.
• Perform deep-dive bottleneck analysis and implement performance and memory optimizations in C/C++.
• Write technical specifications and unit tests for delivered code.
• Collaborate with a global, distributed team to deliver high-quality results.

Requirements

Key technical skills and experience required. Items labeled "Nice-to-have" indicate preferred but not mandatory qualifications.

• Must-have: 5+ years of EDA software development experience.
• Must-have: Strong proficiency in C/C++ and experience implementing performance optimizations.
• Must-have: Deep understanding of SystemVerilog or Verilog and RTL/logic simulation concepts.
• Must-have: Experience with SDC constraints, timing analysis, and path-exception handling in STA tools.
• Must-have: Experience with multi-threaded and concurrent programming.
• Must-have: Ability to write specifications and unit tests; perform detailed performance profiling and bottleneck resolution.
• Nice-to-have: Experience designing or tuning graph algorithms at very large scale (multi‑billion-node graphs).
• Nice-to-have: Prior experience specifically on RTL/logic simulator development.

Education Requirements

MS in Computer Science or Electrical Engineering (typically with ~7+ years of relevant experience) or PhD in Computer Science or Electrical Engineering (typically with ~5+ years of relevant experience). Specific degree requirements were stated in the source posting.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.