Senior Principal Software Engineer - Compiler Development

Job Title

Senior Principal Software Engineer - Compiler Development

Role Summary

Develop and optimize the Xcelium SystemVerilog compiler and code generator to enable verification of very large, complex chip designs. The role focuses on compiler front-end, intermediate representations, code generation, and performance engineering for the logic simulator.

Team: Compiler and build performance group in the System Verification organization; mission is to improve compile speed, memory footprint, and scalability for AI and hyperscale designs.

Experience Level

Senior (Principal) — requires substantial industry experience in compiler development, EDA, or high-performance computing. See Education Requirements for years-based qualifications.

Responsibilities

Work includes language design, compiler architecture, and performance improvements across large codebases.

• Design and implement SystemVerilog language extensions and related compiler features.
• Develop and optimize front-end and code generation components, including intermediate representations that scale to very large designs.
• Identify bottlenecks and implement performance and memory-usage optimizations in C/C++.
• Architect compiler and simulator components to handle massive replicated and parallel structures found in modern AI chips.
• Research and prototype new ideas such as LLM-assisted compilation, parallel and distributed compilation approaches.

Requirements

Must-have:

• Expert-level C++ (modern standards) with demonstrated, production-grade use.
• Deep practical experience with SystemVerilog or Verilog and compiler theory (lexing, parsing, semantic analysis, code generation).
• Experience in compiler development, EDA, or high-performance computing (multiple years of hands-on work in these areas).
• Strong knowledge of multithreading, memory management, and cache-locality optimizations for performance-sensitive systems.
• Proven ability to analyze performance bottlenecks and implement scalable solutions.

Nice-to-have:

• Familiarity with LLVM or other compiler frameworks.
• Experience with Python for tooling and test automation.
• Familiarity with hardware verification environments such as UVM.
• Experience with distributed or parallel compilation and prototype research projects (e.g., LLM enhancements).

Education Requirements

Posting specifies degree plus experience options: BS with a minimum of 10 years' relevant experience, MS with a minimum of 7 years, or PhD with a minimum of 5 years; or equivalent practical experience. No specific field-of-study or certifications were listed.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.