Senior Principal High-Speed I/O Architect (PCIe, CXL, UA Link)
ArmJob Title
Senior Principal High-Speed I/O Architect (PCIe, CXL, UA Link)
Role Summary
The High-Speed I/O Architect designs on-chip interconnect and high-speed I/O subsystems (PCIe, CXL, UA Link) for scalable SoC platforms across markets including mobile, automotive, datacenter, networking, and IoT.
The role partners with SoC architects, performance/power/physical-design teams, and software/firmware teams to produce implementation-ready specifications and to optimize system-level bandwidth, latency, and efficiency.
Experience Level
Senior - the role expects senior-level experience. The posting references 8+ years for protocol/coherency work and indicates preferences consistent with 10+ years for semiconductor architecture roles.
Responsibilities
Primary responsibilities include defining architecture and collaborating across teams to deliver high-speed I/O subsystems and SoC-level solutions.
- Architect high-speed interconnect subsystems (PCIe, CXL, UA Link) including coherent and non-coherent communication models.
- Define IP and subsystem roadmaps in partnership with SoC architecture and core-technology teams.
- Lead early customer architecture engagements and produce implementation-ready specifications.
- Collaborate with performance, power, and physical-design teams to optimize subsystem behavior, bandwidth, latency, and system efficiency.
- Develop SoC-level architecture integrating Arm IP and high-speed I/O to meet compute, memory, and interconnect targets.
- Partner with software, firmware, and platform teams to optimize end-to-end hardware/software solutions.
- Perform use-case exploration, workload analysis, and performance modeling to guide architectural trade-offs.
Requirements
Concise list of must-have technical skills and preferred traits. Degrees and formal education requirements are summarized under Education Requirements below.
- Must-have: Deep technical expertise with PCIe, CXL, and UA Link protocols, including link-level behavior, transaction flows, ordering models, memory expansion/pooling, die-to-die/chiplet connectivity, and host/device integration.
- Must-have: Strong background in coherency protocols, hierarchical cache design, and system-level coherency architectures; demonstrated collaboration with performance, power, and physical-design teams.
- Must-have: Experience defining IP/subsystem roadmaps and delivering architecture-level specifications for silicon products.
- Must-have: Proven communication and leadership skills with ability to influence executive and multi-functional stakeholders.
- Nice-to-have: Track record of delivering complex projects to specification on schedule; ability to adapt in dynamic environments and improve existing approaches.
Education Requirements
Bachelor's or Master's degree in Electrical or Computer Engineering (or equivalent practical experience). The posting explicitly allows "or equivalent" and references semiconductor architecture/design experience.
About the Company
Company: Arm
Headquarters: Cambridge, United Kingdom
ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.
