Senior Principal Engineer, Subsystem CoE Emulation

Job Title

Senior Principal Engineer, Subsystem CoE Emulation

Role Summary

Lead development and execution of scalable emulation infrastructure and pre-silicon validation for complex SoC subsystems within the Custom Compute and Storage (CCS) Business Unit Emulation Center of Excellence.

Work closely with RTL design, verification, firmware, and software teams to deliver emulation models, enable firmware bring-up, validate high-speed and memory interfaces, and support system-level debug and software readiness.

Experience Level

Senior — experienced individual contributor and technical leader. Posting indicates senior principal expectations (typically 15+ years of relevant industry experience).

Responsibilities

Primary responsibilities include building, running, and improving emulation environments and leading cross-functional debugging and validation efforts.

• Lead development of complex SoC emulation models, integration, environment setup, compilation, and debug on platforms such as Veloce, ZeBu, Palladium.
• Drive emulation bring-up: clock/reset sequencing, firmware boot, and system validation using pre-silicon hardware models.
• Create and execute emulation test plans supporting verification, performance analysis, software development, and system validation.
• Collaborate with RTL, verification, and firmware teams to define requirements and ensure accurate hardware model integration.
• Debug complex SoC and subsystem issues across RTL, firmware, emulation platforms, and toolchains.
• Optimize emulation performance: model partitioning, timing, and runtime efficiency.
• Automate flows and improve productivity through scripting and tooling enhancements.
• Interface with EDA vendors to evaluate tools, resolve technical issues, and drive feature improvements.
• Define and execute emulation strategy for subsystems including boot, security, PCIe, CXL, DDR, HBM, USB, Ethernet, and peripherals.

Requirements

Must-have technical skills, domain expertise, and situational requirements for this role.

• Strong, hands-on experience in SoC emulation, validation, and debug.
• Expertise in one or more domains: boot/system initialization, security architecture and validation, high-speed protocols (PCIe, CXL, Ethernet), memory interfaces (DDR, HBM), and peripheral interfaces (SPI, I2C, UART, USB 3.0).
• Proven hands-on experience with emulation platforms (Palladium, ZeBu, Veloce) and system-level bring-up.
• Strong debugging skills across hardware/software boundary and familiarity with RTL/firmware interactions.
• Proficiency in scripting and automation (Python, Perl, Tcl, Shell) to create and maintain emulation flows and tools.
• Proven ability to lead cross-functional technical efforts and drive execution to completion.
• Experience optimizing model performance, partitioning, and improving runtime efficiency.
• Ability to interface with EDA vendors and evaluate tool capabilities.
• Must be eligible to access export-controlled technology and information; candidates may be subject to export license review prior to employment.

Education Requirements

Bachelor’s degree with 18+ years, or Master’s/PhD with 15+ years in Electrical Engineering, Computer Science, or a related field; equivalent practical experience may be considered.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.