Senior Principal Engineer - RTL

Job Title

Senior Principal Engineer - RTL

Role Summary

Lead subsystem architecture and delivery for advanced SoC subsystems, focusing on reusable end-to-end designs and ease of integration across product lines.

Work across SoC engineering, product architecture, verification, firmware/software and system teams; own roadmap, standards adoption, KPI definition, and provide technical leadership and mentorship.

Experience Level

Senior. Guidance: typically 20+ years of relevant professional experience (or 18+ years with a Master's/PhD as noted in Education Requirements).

Responsibilities

Key responsibilities include subsystem architecture, roadmap ownership, and cross-team delivery.

• Define and drive subsystem architecture, standards adoption, and design trade-offs to meet performance, power, security and scalability KPIs.
• Own subsystem roadmap, specifications (architecture, micro-architecture, registers) and product requirement documents.
• Produce integration collateral: integration guides, reference designs, performance models, benchmarks and limits.
• Define verification strategy at subsystem level and collaborate with verification teams on test plans, full-chip simulation/emulation, performance and power analysis, and debug.
• Collaborate with third-party IP vendors to define customization, requirements and IP integration approach.
• Coordinate tightly with SoC chief engineers, product architecture, DFT, firmware/software, and system teams during design and bring-up.
• Mentor and provide technical guidance to junior and mid-level engineers.

Requirements

Must-have technical skills and experience. Nice-to-have items noted.

• Must-have: Proven experience creating architectural, micro-architectural, and register specifications.
• Must-have: Verilog/SystemVerilog RTL coding and SystemVerilog assertions (SVA).
• Must-have: Deep familiarity with all stages of the ASIC design flow, including architecture, design implementation and prototype bring-up.
• Must-have: Experience owning subsystem and block-level architecture on complex chips (network processors, CPUs, GPUs, NOCs, switches, ML SoCs, etc.).
• Must-have: Experience with peripheral interface IPs and protocols such as I3C, I2C, SPI/QSPI, UART, GPIO and USB.
• Must-have: Experience integrating third-party IP from vendors (Synopsys, Cadence, ARM) and performing subsystem-level customization and integration.
• Must-have: Knowledge of interconnect fabrics and protocols (AXI/APB, NoC, Arm/Arteris fabrics).
• Must-have: Scripting and automation skills (Perl, Python, Shell) and practical use of AI-assisted tools for productivity/automation.
• Must-have: Proven ability to define verification strategy and collaborate with verification teams on simulation, emulation, performance and power analysis.
• Nice-to-have: Experience developing performance models, benchmarks, limits, and reference designs for subsystem integration.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering or related field with ~20+ years of related professional experience; OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related field with ~18+ years of related experience; equivalent practical experience will be considered. Candidates may be subject to export-control eligibility review.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.