Senior Principal Engineer, Hardware Application Engineering - Signal Integrity & Power Integrity

Job Title

Senior Principal Engineer, Hardware Application Engineering - Signal Integrity & Power Integrity

Role Summary

Senior individual contributor in Marvell's U.S. Customer Solutions Group responsible for ensuring customer platforms using Marvell Ethernet switch and UALink silicon meet SI and PI performance and quality targets from prototype through mass production.

Works directly with customers, ODMs, and internal silicon and hardware teams to define layout guidelines, run post-silicon simulations and lab characterization, provide SerDes tuning and PDN guidance, and feed learnings back into product and platform roadmaps.

Experience Level

Senior-level. Typical candidate has 15+ years in hardware design and 10+ years focused on signal integrity and power integrity for high-speed SerDes platforms.

Responsibilities

Primary responsibilities include technical authority, simulation, testing, and customer enablement:

• Act as senior SI/PI authority for Marvell-based customer platforms from channel definition through production qualification.
• Define and drive adoption of layout, routing, and stack-up guidelines for high-speed SerDes channels and PDNs.
• Perform post-silicon channel extraction, full-channel simulation, and what-if analysis; recommend layout and stack-up fixes.
• Lead compliance testing and lab characterization (BER/SER, eye margins, jitter, return loss, crosstalk) and translate results into design and tuning guidance.
• Provide SerDes tuning guidance and partner with silicon teams to refine tuning methods.
• Run and review PI simulations (PDN impedance, IR drop, decoupling, transient response) and advise on PDN architectures for high-current ASICs.
• Engage with ODMs on design reviews, qualification activities, and high-volume manufacturing considerations.
• Support reference design definition and own SI/PI through customer release; provide hands-on lab debug during bring-up and ramp.
• Develop and deliver SI/PI training to customers, ODMs, and internal teams; represent SI/PI expertise in customer and industry forums.

Requirements

Must-have skills and experience; preferred items listed separately.

• 15+ years total hardware design and validation experience; ~10+ years focused on SI/PI for high-speed SerDes platforms (25G NRZ to 112G/224G PAM4).
• Proven full SI lifecycle capability: channel modeling/budgeting, post-layout extraction and simulation, design fixes, compliance and tuning guidance.
• Strong PI skills: PDN simulation, IR drop analysis, decoupling strategy, transient/droop analysis.
• Fluency with leading SI/PI EDA toolchains (Ansys HFSS/SIwave, Cadence Sigrity/Clarity/PowerSI, or equivalent) and ability to learn required tools.
• Hands-on lab expertise with VNAs, BERTs, oscilloscopes (real-time/sampling), TDR, jitter analyzers, and compliance test kits.
• Customer-facing experience supporting complex technical engagements and production deployments; excellent communication and influencing skills.
• Ability to develop technical training and mentor engineers; travel to customer sites and labs as needed.
• Preferred: direct experience with Ethernet switch platforms, open AI fabric standards, megascale data center deployments, ODM/CM qualification flows, and SerDes tuning methodology development.

Education Requirements

PhD, Master’s, or Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field. The posting also notes that exceptionally talented candidates with fewer years of experience but demonstrated mastery are encouraged to apply.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.