Senior Principal Engineer, DFT

Job Title

Senior Principal Engineer, DFT

Role Summary

Lead the definition and deployment of Design-for-Test (DFT) architectures and methodologies across Arm CPUs, GPUs, system IP, AI accelerators and complex SoCs. Work with product teams, architects, design engineers and EDA vendors to define scalable, reusable DFT solutions ahead of production.

This is a technical architecture role with cross-organizational influence and responsibility for methodology, implementation flows and industry engagement.

Experience Level

Senior-level (Principal / Senior Principal). The role expects extensive hands-on and architecture-level DFT experience; years of experience not explicitly specified.

Responsibilities

Primary responsibilities include:

• Define DFT architecture for next-generation IPs and SoCs, including AI and hyperscale products.
• Develop and drive scalable DFT methodologies and implementation flows used across multiple engineering organizations.
• Evaluate emerging DFT technologies and lead technical investigations to solve future product challenges.
• Collaborate with architecture, implementation, verification and physical design teams to define robust DFT solutions.
• Engage with EDA vendors to influence roadmaps, evaluate capabilities and drive technology adoption.
• Produce architecture specifications, methodology documentation and deployment guidance.
• Provide technical leadership, mentorship and support strategic engagements with customers, ASIC partners and standards bodies.
• Contribute to technical publications, patents and industry conferences where appropriate.

Requirements

Must-have skills and experience:

• Proven Principal or Senior Principal-level experience in DFT architecture and implementation.
• Deep knowledge of modern SoC DFT methodologies, including scan architecture and scan compression, ATPG and fault simulation, at-speed testing, memory BIST, logic BIST, JTAG (IEEE 1149.1), IJTAG (IEEE 1687), and DFT verification/debug.
• Experience developing reusable DFT methodologies or automation rather than project-specific solutions.
• Experience evaluating and deploying Siemens Tessent, Synopsys and/or Cadence DFT solutions.
• Strong scripting skills (Perl, Tcl and/or Python) and Linux/Unix expertise.
• Strong analytical and problem-solving skills, with the ability to influence technical direction across multiple teams.

Nice-to-have:

• DFT architecture experience for large-scale SoCs, heterogeneous compute systems, AI accelerators or hyperscale products.
• Knowledge of IEEE 1500, IEEE 1838, advanced IJTAG methodologies, Streaming Scan Network (SSN), and chiplet/3DIC architectures.
• Familiarity with silicon bring-up, production test, synthesis, STA, physical implementation considerations for DFT, formal verification and simulation methodologies.
• Experience working directly with EDA vendors on new technology development and a record of patents or conference publications.

Education Requirements

Degree (or equivalent) in Electronic Engineering, Computer Engineering or a related discipline. Equivalent practical experience is explicitly accepted.

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.