Senior Principal Engineer, Chip Lead, Photonic Fabric Chiplet

Job Title

Senior Principal Engineer, Chip Lead, Photonic Fabric Chiplet

Role Summary

The Chip Lead will own end-to-end development of a heterogeneous photonic chiplet that integrates a high-speed electrical IC (with advanced analog SERDES) and a photonic integrated circuit (PIC) using advanced co-packaged technologies. The role leads cross-functional teams across die, package, optics, firmware and system domains from architecture through silicon bring-up, ATE and system validation.

Work is focused on enabling high-bandwidth, low-latency optical interconnects for data center and AI accelerator systems.

Experience Level

Senior — requires extensive hands-on technical leadership and program ownership. Guidance from posting: senior-level experience (see Education Requirements for the explicit experience/degree combinations).

Responsibilities

Primary responsibilities include technical ownership across electrical, photonic, firmware, packaging and system validation domains and leading delivery of complex silicon products.

• Own end-to-end product design spanning Electrical IC, Photonic IC, firmware stack, and advanced packaging.
• Lead micro-architecture and RTL development for electrical ICs including high-speed SERDES and digital subsystems.
• Collaborate with verification teams to ensure robust functional and performance verification across digital RTL, AMS and electrical-optical interfaces.
• Work with physical design and packaging teams on floorplanning, implementation, timing, power, and physical verification closure.
• Define and drive DFT strategy for digital, analog SERDES, and system-level testability.
• Partner with photonics teams to define PIC architecture, interfaces, and electrical–optical co-design.
• Collaborate with test engineering to enable ATE, develop test programs, and support test debug.
• Lead cross-functional system-level validation including boards, optics, firmware and software interaction; drive root-cause analysis across silicon, package, optics and system domains.
• Mentor and develop senior engineers and influence cross-functional teams; communicate technical status, risks and tradeoffs to engineering and product leadership.

Requirements

Core must-have skills and experience for effective performance in the role.

• Extensive ASIC/SoC development experience with demonstrated end-to-end chip ownership (program-level responsibility for design through production).
• Expertise in micro-architecture and RTL design for high-speed interfaces and digital subsystems.
• Proven experience with mixed-signal design, AMS verification, and electrical–optical interface design.
• Deep knowledge of high-speed analog SERDES, physical design, timing/power closure and sign-off practices.
• Hands-on experience with DFT, manufacturing test practices, ATE enablement and test program development.
• Experience with advanced packaging, chiplet-style integration, post-silicon bring-up and system validation.
• Strong ability to articulate architectural tradeoffs (performance, power, area, yield, cost, schedule, risk) and to drive alignment across matrixed teams.
• Excellent written and verbal communication skills, including presenting technical reviews to executive leadership.

Nice-to-have:

• Prior delivery of high-speed I/O and/or optical products into production.
• Previous experience as a Chip Lead, SoC Architect, or System-Level Technical Lead.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related field with 15+ years of related professional experience; or a Master's degree / PhD in Computer Science, Electrical Engineering or related fields with approximately 8–12 years of related experience. Equivalent practical experience is accepted where stated.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.