Senior Principal Engineer

Job Title

Senior Principal Engineer

Role Summary

Lead technical architect responsible for defining and advancing FPGA physical synthesis, timing optimization, and implementation methodologies. The role drives algorithmic innovation, QoR improvements, runtime and scalability for large-scale FPGA and ASIC implementation flows.

Works across synthesis, placement, routing, timing analysis, and product teams to deliver production-quality EDA tooling and mentor engineering teams.

Experience Level

Senior - typically 15+ years of relevant experience in EDA, FPGA tools, ASIC implementation tools, or related optimization technologies.

Responsibilities

Primary technical leadership and delivery responsibilities.

• Define and drive architectural roadmap for FPGA compiler and implementation technologies.
• Design and implement advanced optimization algorithms for timing closure, area, power, routability, and runtime.
• Lead development of timing-driven optimization methodologies and physical synthesis improvements.
• Architect scalable solutions for large hierarchical designs and complex implementation flows.
• Integrate new technologies into production tool flows with cross-functional engineering teams.
• Analyze customer workloads and benchmarks to identify high-impact improvements.
• Investigate and resolve challenging timing and implementation problems across customer designs.
• Mentor engineers and provide technical leadership across architectural initiatives.
• Collaborate with product management and strategic customers to translate needs into technology direction.
• Contribute to patents, publications, and industry-facing technical leadership.

Requirements

Must-haves and useful experience for success in this role.

• Must-have: 15+ years developing EDA software, FPGA tools, ASIC implementation tools, or related optimization technologies.
• Must-have: Deep expertise in one or more domains: physical synthesis, timing analysis, logic synthesis, placement & routing, static timing analysis, design optimization algorithms, FPGA architecture and CAD flows.
• Must-have: Strong software development skills in C++, data structures, algorithms, and performance optimization; experience architecting large-scale software systems.
• Must-have: Proven ability to solve complex technical problems and deliver innovations into production tools; experience influencing technical direction across teams.
• Must-have: Eligible for any required U.S. export authorizations.

• Nice-to-have: Commercial experience developing FPGA or ASIC implementation tools; path-based optimization or timing-driven synthesis expertise.
• Nice-to-have: Experience improving tool QoR, runtime, or scalability for large customer designs; machine learning applications for EDA.
• Nice-to-have: Patent portfolio or significant technical publications; prior role as Distinguished Engineer, Architect, Fellow, or equivalent.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related technical field.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.