Senior Principal Engineer, Analog Design (HBM PHY)

Job Title

Senior Principal Engineer, Analog Design (HBM PHY)

Role Summary

Senior technical leader responsible for analog and mixed-signal architecture, design, and silicon bring-up of HBM PHY solutions. Embedded in a central analog engineering team, the role drives PHY circuit architecture and high-speed interface performance across system, digital, and packaging domains.

Experience Level

Senior — requires 15+ years of experience in analog/mixed-signal IC design with a focus on high-speed interfaces.

Responsibilities

Lead architecture, design, verification, and bring-up activities for HBM PHY analog and mixed-signal blocks.

• Define and own analog/mixed-signal PHY architecture (TX/RX, clocking, DLL/PLL, references).
• Design high-speed IO drivers, receivers, equalization, clock distribution, and timing circuits.
• Establish and enforce SI, PI, jitter, and noise budgets across the PHY and system.
• Drive training, calibration engines, margining support, and co-design with logic/RTL teams.
• Lead design reviews, modeling, AMS/system-level simulation, and verification methodologies.
• Plan and execute silicon bring-up, post-silicon characterization, debugging, and root-cause resolution.
• Collaborate with physical design, packaging, SI/PI, and system architecture teams to ensure robust PVT and variation coverage.
• Engage with memory vendors and ecosystem partners to validate interoperability and compliance.

Requirements

Core technical requirements and relevant skills. Education-related items are summarized in the Education Requirements section below.

• 15+ years in analog/mixed-signal IC design with significant emphasis on high-speed interfaces.
• Proven track record of delivering silicon-proven PHYs or SerDes at advanced process nodes.
• Deep expertise in high-speed IO design: TX/RX circuits, equalization, clocking, and jitter optimization.
• Strong mixed-signal experience: DLLs, PLLs; CDR experience preferred.
• Solid understanding of signal integrity, power integrity, jitter/noise, and channel effects.
• Experience with packaging and interconnect impacts (2.5D/3D integration, interposers).
• System-level modeling and AMS/behavioral co-simulation experience.
• Proven ability to lead cross-functional teams and to debug complex silicon issues through to resolution.

Nice-to-have:

• Experience with HBM PHY or memory interfaces (HBM3/HBM4).
• Background in SerDes, DDR/LPDDR/GDDR PHY design and equalization/training/DFE concepts.
• Exposure to advanced packaging, chiplets, and interposer-based integration.
• Prior interaction with memory vendors and system-level integration teams.

Education Requirements

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Science, or a related technical field (as stated in the posting).

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.