Senior Principal Digital IC Design Engineer

Job Title

Senior Principal Digital IC Design Engineer

Role Summary

Member of the Data Center Engineering group responsible for digital design of high-performance mixed-signal ICs used in high-speed interconnects for hyperscaler data centers. Deliver micro-architecture, RTL, and reusable IP that meet strict performance, power, and latency requirements for AI cluster communications.

Experience Level

Senior-level. See Education Requirements for the role's degree and years-of-experience guidance.

Responsibilities

Accountable for end-to-end digital block delivery from micro-architecture through silicon bring-up and maintenance.

• Design, implement, verify, and document micro-architecture and RTL for complex power management and high-performance blocks.
• Collaborate with system and chip architects to produce industrial-quality implementations.
• Participate in the full design cycle: author micro-architecture docs, RTL coding, timing specifications, and review test plans with verification teams.
• Bring up block tests on silicon during lab validation and maintain delivered blocks and reusable IP.
• Produce comprehensive block micro-architecture and register specifications.
• Schedule and lead detailed cross-functional design and verification reviews.
• Evaluate and improve design and verification methodologies.
• Supervise or mentor other digital design engineers.

Requirements

Key technical skills and experience required or preferred for effective performance in the role.

• Must-have: Extensive experience with Verilog/SystemVerilog, synthesis flows, static timing analysis (STA), and low-power design methodologies.
• Must-have: Experience with RTL quality checks and tools (linting, CDC analysis, e.g. Spyglass or equivalent).
• Must-have: Hands-on scripting experience (Perl, Python) for automation and flow support.
• Must-have: Proven record of delivering production-quality designs on aggressive schedules; experience collaborating with verification teams and supporting silicon bring-up.
• Nice-to-have: Domain expertise in 802.3 standards and SerDes design.
• Nice-to-have: Background in digital signal processing, error correction codes, and physical-layer protocols.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related technical field with 12+ years of relevant experience; or Master's degree in Electrical Engineering or related field with 10+ years; or PhD in Electrical Engineering/Electrical and Computer Engineering or related field with 5+ years. Related technical degrees in CS, EE, or ECE are acceptable.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.