Senior Principal Design Verification Engineer - FPGA (Sign-on Bonus)

Job Title

Senior Principal Design Verification Engineer - FPGA (Sign-on Bonus)

Role Summary

Lead development and execution of FPGA design verification for electronic warfare systems. You will plan and build verification architectures, develop automated, metric-driven testbenches, and lead small-to-medium DV teams across multiple U.S. locations.

This is an on-site engineering role focused on improving verification methodology, creating reusable verification IP, and delivering verified FPGA designs for mission-critical defense systems.

Experience Level

Senior-level - typically 8+ years of relevant work experience (posting specifies 8+ years or equivalent experience).

Responsibilities

Primary responsibilities include:

• Plan, architect, develop, and maintain configurable self-checking testbenches using SystemVerilog/UVM, OVM, and/or VHDL.
• Design and execute constrained-random, metric-driven test plans for FPGA signal-processing and control functions.
• Collect and analyze coverage and verification metrics and iterate on testcases to improve coverage.
• Lead and mentor small-to-medium DV teams; coordinate work across multiple U.S. locations.
• Create reusable Verification IP for organization-wide use.
• Drive process and methodology improvements in verification practices.
• Document verification strategies, test plans, and results; communicate status and risks to program stakeholders.

Requirements

Must-have skills, experience, and conditions:

• Must be a U.S. person; U.S. citizenship is required for clearance eligibility.
• Ability to obtain and/or maintain a U.S. Secret security clearance.
• Experience planning, architecting, developing, and using constrained-random, self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL.
• Familiarity with FPGA/ASIC design and verification tools (examples: Mentor Questa, Cadence).
• Proven record of managing schedules, executing tasks to closure, and supporting multiple projects concurrently.
• Strong written and verbal communication and documentation skills.
• Experience developing and implementing verification test plans and measuring coverage-driven progress.
• Ability to work effectively in multi-site engineering teams.

Preferred / nice-to-have:

• Perl or Python scripting.
• C++ or Java experience.
• Version control and issue-tracking tools (Git, Jira, BitBucket).
• Digital Signal Processing experience and Matlab/Simulink familiarity.
• Working knowledge of VHDL and FPGA design implementation experience.
• Experience creating reusable Verification IP, leading teams with responsibility for cost/schedule/quality, and driving process improvements.

Education Requirements

Bachelor's degree plus 8+ years of relevant experience, or equivalent practical experience. No specific field-of-study was mandated in the posting.

About the Company

Company: BAE Systems

Headquarters: London, United Kingdom

Global defense, aerospace and security company delivering products and services for air, land and naval forces, advanced electronics, cyber and intelligence solutions, and space and mission systems for government and commercial customers.