Senior Principal Design Verification Engineer
RenesasJob Title
Senior Principal Design Verification Engineer
Role Summary
Lead verification for the Automotive PMIC product line by defining verification strategy, architecting mixed-signal verification environments, and mentoring verification engineers. Collaborate with design, ATE, application engineering, and silicon validation to ensure functional, timing, and power correctness across domains.
Experience Level
Senior — typically 12+ years of mixed-signal or analog verification experience.
Responsibilities
Primary responsibilities include designing verification architectures, driving verification plans, and leading debugging and cross-team coordination.
- Architect and implement mixed-signal verification environments, including RNM and AMS integration for PMIC designs
- Develop and execute verification plans and strategies aligned with automotive standards (ISO 26262, AEC-Q200)
- Set up and optimize gate-level simulation (GLS) flows and correlate GLS with RTL simulation
- Perform RTL and gate-level simulations across PVT corners; analyze timing, power, and functionality
- Debug complex analog blocks (switched-mode regulators, LDOs, bandgaps) and analog-digital interactions using simulation and measurement techniques
- Collaborate with Design, ATE, Application Engineering, and Silicon Validation for verification handoffs and test correlation
- Mentor and lead junior verification engineers; define and enforce verification best practices
- Drive continuous improvement of verification tools, methodologies, and infrastructure
- Create and maintain verification documentation, test plans, and coverage artifacts
Requirements
Must-have technical skills and experience for this role.
- 12+ years in mixed-signal or analog circuit verification
- Deep knowledge of mixed-signal verification environment architecture and implementation
- Hands-on experience with Real Number Model (RNM) and AMS model integration
- Proficiency with RTL and behavioral simulation tools (e.g., Spectre, Xcelium)
- Experience setting up and debugging GLS simulations
- Strong skills in Verilog, SystemVerilog, and SPICE-based languages
- Familiarity with verification methodologies: UVM, assertions, and coverage-driven verification
- Experience with automotive PMIC or power-management IC verification and ATE/test correlation
- Proven debugging, analytical problem-solving skills, and leadership/mentoring experience
Nice-to-have:
- Experience with post-silicon validation and ATE integration
- Exposure to AI-assisted verification tools
Education Requirements
MS or PhD in Electrical Engineering, Computer Engineering, or a related technical field (as stated in the posting).
About the Company
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.
