Senior Principal Design Engineer

Job Title

Senior Principal Design Engineer

Role Summary

Responsible for design, development, verification, and long-term support of system-level memory IP models used in hardware-based verification platforms. Works across memory technologies and interfaces and collaborates with internal teams and external customers to resolve emulation, simulation, and verification challenges.

This is a senior individual-contributor role focused on high-quality RTL, verification strategy, debugging, documentation, and product maintenance.

Experience Level

Senior — posting specifies a minimum of 5 years of significant experience designing complex protocols, RTL, and/or hardware systems.

Responsibilities

Primary responsibilities include design, verification, maintenance, and customer support for system-level memory IP models.

• Design, develop, verify, and productize system-level memory IP models for hardware-based verification platforms.
• Develop models for LPDDR, HBM, NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS.
• Develop high-quality Verilog/SystemVerilog RTL and follow sound design and coding practices.
• Develop and execute verification strategies using industry-standard simulation and emulation tools and methodologies.
• Diagnose and resolve complex RTL, protocol, system, and customer issues through debugging and root-cause analysis.
• Maintain and enhance existing memory IP products for performance, quality, usability, and customer support.
• Create and maintain technical documentation, design specifications, and product support materials.
• Work directly with internal and external customers to understand requirements and investigate issues.
• Plan and manage individual project schedules, priorities, deliverables, and technical tasks.
• Collaborate with cross-functional teams to support cross-verification, knowledge sharing, and process improvements.

Requirements

Must-have technical skills and experience; preferred skills listed separately.

• Must-have: Extensive hands-on Verilog/SystemVerilog RTL design experience.
• Must-have: Strong understanding of RTL verification methodologies, tools, and flows.
• Must-have: Demonstrated ability to debug complex hardware, RTL, protocol, and system-level issues.
• Must-have: Strong analytical, problem-solving, written and verbal communication, and organizational skills.
• Must-have: Proven ability to work effectively as an individual contributor and collaborate with engineering, product, and customer-facing teams.
• Preferred: Experience with Cadence simulation and/or emulation products or other hardware-based verification platforms.
• Preferred: Programming or scripting experience (Perl, Tcl/Tk, C-shell, or similar).
• Preferred: Experience with memory subsystem architecture and protocols (LPDDR, HBM, NAND Flash, eMMC, SD, DFI, UFS).
• Preferred: Experience developing reusable IP models or verification components for SoC or system-level environments.

Education Requirements

Posting specifies MSEE (Master of Science in Electrical Engineering) or an equivalent advanced degree, with a minimum of 5 years of significant experience designing complex protocols, RTL, and/or hardware systems.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.