Senior Principal Design Engineer

Job Title

Senior Principal Design Engineer

Role Summary

Support adoption of Cadence products by chip-design customers, focusing on physical implementation (place & route), synthesis, and signoff to meet design PPA goals. Work on RTL-to-GDSII delivery, competitive benchmarking, and methodology development while providing technical leadership to customers and field teams.

Experience Level

Senior-level — typically requires 7+ years of relevant ASIC implementation or EDA-equivalent experience.

Responsibilities

Primary responsibilities include engineering support, methodology development, and customer technical leadership.

• Lead customer implementations from RTL to GDSII, including block and top-level implementation and signoff.
• Manage strategic customer evaluations and competitive benchmarks to demonstrate technology advantages.
• Develop and improve implementation methodologies for synthesis, placement, routing, CTS, and STA.
• Deliver technical presentations, product demonstrations, and training to customers and internal teams.
• Act as primary technical contact for major regional customers and support adoption of front-end and implementation tools.
• Collaborate with product and sales teams to translate customer needs into product and methodology improvements.

Requirements

Must-have technical skills and experience for immediate contribution. Education expectations are listed separately below.

• Proven ASIC design experience using Verilog and RTL-to-GDS implementation flows.
• Deep knowledge of place-and-route and physical synthesis flows, CTS, and static timing analysis using Cadence or Synopsys tools.
• Experience with Encounter Digital Implementation Platform or equivalent full-flow implementation toolset.
• Experience supporting tapeouts, signoff flows, and meeting PPA targets.
• Strong customer-facing skills: run evaluations, present technical results, and guide tool/methodology adoption.
• Practical scripting skills (TCL/Perl) for design automation and rapid customer solutions.

Nice-to-have: multi-voltage/low-power implementation and clock-tree debugging experience; exposure to CPU/GPU/DSP block implementations and multiple foundry nodes.

Education Requirements

Normally requires a Bachelor's degree (BS) and approximately 7 years of relevant experience; strong technical knowledge of EDA products is expected. Not an entry-level position.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.