Senior Principal Design Engineer

Job Overview

Cadence Design Systems is seeking a Senior Principal Verification Engineer to spearhead verification efforts for advanced IP development, located in Bengaluru, Karnataka, India.

Position Summary

The role involves architecting robust verification environments, improving methodologies, and mentoring junior team members. You will work with design and architecture teams to ensure successful and high-quality project deliverables.

Experience Level

This position requires at least 10 years of experience in IP verification, demonstrating strong leadership and technical skills in a collaborative setting.

Key Responsibilities

• Develop and maintain UVM-based verification environments for IP verification.
• Debug complex IP designs and resolve issues effectively.
• Review and enhance verification test plans for completeness and coverage.
• Drive development of testbenches, simulations, and regression strategies.
• Mentor junior engineers in verification methodologies.
• Collaborate across functional teams for seamless integration.

Required Skills

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a related field.
• Strong proficiency in SystemVerilog and UVM methodology.
• Expertise in debugging complex IP designs.
• Hands-on experience in testbench development and test plan reviews.
• Proven ability to mentor and lead verification teams.

Preferred Skills

• Experience in SERDES verification.
• Familiarity with UCIe protocol and chiplet integration.
• Knowledge of high-speed interfaces and related verification challenges.