Senior/Principal Analog Mixed-Signal Design Engineer, Optical Receiver

Job Title

Senior/Principal Analog Mixed-Signal Design Engineer, Optical Receiver

Role Summary

Design and deliver receiver front-end circuits for high-speed parallel optical links, from specification through post-layout signoff and silicon correlation. Work on dense receiver arrays in a cross-functional team including RX lead, layout, digital and system architecture.

Experience Level

Senior to Principal level. Typical guidance: senior engineers have 5+ years of analog/mixed-signal design experience; principal-level roles generally require ~10+ years and demonstrated technical leadership.

Responsibilities

Primary responsibilities focus on design, verification, and silicon correlation of optical receiver front-end blocks.

• Specify, design and simulate photodetector interfaces, transimpedance amplifiers, limiting and post-amplifiers, equalization, comparators/slicers, offset cancellation and detection circuits.
• Analyze noise, bandwidth, sensitivity, crosstalk and power per lane across PVT corners and Monte Carlo simulations.
• Design calibration and trim circuits and define their control interface with the digital team.
• Collaborate with layout on floorplans, matching and parasitic-sensitive routing for dense arrays; run post-layout extraction and verification.
• Deliver behavioral models (Verilog-A or real-number models) and correlate them with transistor-level results.
• Write block specifications, present at design reviews, support silicon bring-up and correlate measurements with simulation.

Principal-level additional responsibilities:

• Set technical direction for receiver circuits and front-end architecture trade-offs with the RX lead and system architect.
• Lead design reviews, define verification and signoff criteria, and mentor other engineers.

Requirements

Must-have technical skills and experience.

• 5+ years of analog/mixed-signal design experience focused on high-speed receiver circuits (taped-out TIAs, CTLEs, limiting amplifiers or comparators for optical or wireline links).
• Design experience in FinFET or other advanced CMOS processes.
• Proficiency with Cadence Virtuoso and Spectre, including noise, AC, transient and Monte Carlo analysis.
• Experience taking blocks through post-layout extraction and signoff.
• Ability to produce and validate behavioral models and correlate them with silicon results.

Preferred:

• Experience with optical receivers, photodiode interfaces, multi-Gb/s wireline receivers or arrays of parallel lanes.
• Behavioral modeling in Verilog-A or SystemVerilog real-number models; hands-on lab characterization experience.
• MATLAB or Python for analysis and automation.
• 10+ years with technical leadership of receiver designs for principal-level candidates.

Education Requirements

MS or PhD in Electrical Engineering preferred; BS acceptable with equivalent practical experience. Fields: Electrical Engineering or related technical disciplines; equivalent experience considered.

About the Company

Company: Avicena

Headquarters: Sunnyvale, CA, USA

Avicena develops high-speed parallel optical interconnects using microLED transmitters and photodetector receiver arrays, focusing on analog mixed-signal receiver front-ends for dense, multi-lane optical links.