Senior Principal Analog Lead – HBM PHY

Job Title

Senior Principal Analog Lead – HBM PHY

Role Summary

Lead analog/mixed-signal architecture, design, and silicon bring-up for high-bandwidth memory (HBM) PHYs targeting AI, HPC, and hyperscale platforms. The role sits in Central Engineering AMS-IP and requires cross-functional coordination with digital, physical design, packaging, SI/PI, and system teams.

Experience Level

Senior — typically 15+ years of experience in analog/mixed-signal IC design with significant ownership of high-speed interface PHYs or SerDes.

Responsibilities

Technical leadership and end-to-end delivery of HBM PHY analog and mixed-signal solutions.

• Define and own analog/mixed-signal PHY architecture: TX/RX, clocking, DLL/PLL, references, calibration and training assist circuits.
• Design and drive critical high-speed blocks: IO drivers, receivers, equalization, clock distribution, and timing circuits.
• Establish and enforce SI, PI, jitter, and noise budgets; account for package and interconnect impacts.
• Collaborate with RTL/logic architects on training flows, calibration algorithms, and system integration.
• Lead design reviews, modeling/simulation methodologies (including AMS and system-level modeling), and verification for PVT corners and variation.
• Drive post-silicon bring-up, characterization, debug, and root-cause resolution for high-speed interfaces.
• Engage with memory vendors and ecosystem partners to ensure interface compliance and interoperability.

Requirements

Core technical skills, demonstrated delivery, and leadership in high-speed analog/mixed-signal IC design.

Must-have

• 15+ years of hands-on analog/mixed-signal IC design experience with a strong focus on high-speed interfaces.
• Track record of delivering silicon-proven PHYs or SerDes at advanced process nodes.
• Expertise in high-speed IO design: TX/RX circuits, equalization, clocking, and jitter optimization.
• Experience with DLLs/PLLs, CDR (preferred), voltage references, and mixed-signal blocks.
• Strong understanding of signal integrity, power integrity, jitter/noise, and channel effects; experience with package/interconnect (2.5D/3D) impacts.
• System-level modeling and AMS/behavioral co-simulation experience.
• Proven ability to lead cross-functional teams and diagnose complex silicon issues.

Nice-to-have

• Prior HBM PHY or memory interface experience (HBM3/HBM4).
• Background in SerDes, DDR/LPDDR/GDDR PHY design and advanced packaging (chiplets, interposers).
• Familiarity with training/DFE concepts, equalization techniques, and memory vendor collaboration.

Education Requirements

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Science, or a related technical field — or equivalent practical experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.