Senior Power Integrity Co-Design Engineer

Job Title

Senior Power Integrity Co-Design Engineer

Role Summary

Join the SCG ArchDesign team to architect and deliver di/dt mitigation across silicon, package, board, and platform. The role translates product voltage-noise targets into shipped specifications and feeds silicon findings back into next-generation design.

The position requires systems-level thinking, cross-functional coordination across architecture, circuit, ASIC, and platform teams, and pragmatic use of AI tools to accelerate engineering work while maintaining measurement rigor.

Experience Level

Senior. Candidates are expected to have substantial, demonstrated domain experience; the posting indicates guidance of 12+ years in silicon power integrity, voltage noise, or PDN.

Responsibilities

Key responsibilities include:

• Define product-level voltage-noise targets, drive closure, and sign them off at shipment.
• Architect voltage-noise mitigation across the full stack (silicon, package, board, platform) and lead co-design tradeoffs.
• Co-design noise features with Speed/Power/Reliability, circuit, power-architecture, ASIC, and platform teams.
• Build and lead the Sim-to-Si correlation methodology for voltage noise and own correlation rigor.
• Model and prototype next-generation noise features such as transient sensing, droop response, and mitigation IP.
• Lead resolution of show-stopper noise issues during bring-up and characterization.
• Drive architecture-level tradeoffs across voltage/frequency, power, noise, reliability, and thermal boundaries.

Requirements

Must-have technical skills and experience:

• Deep expertise in at least one: di/dt analysis and mitigation, voltage droop, PDN design (die + package + board), transient noise, or decoupling budgeting.
• Hands-on silicon bring-up and characterization experience; comfortable using oscilloscopes, probes, DAQ, and simulators.
• Strong Sim-to-Si correlation instincts and the independence to challenge models or measurements.
• Proven application of AI/ML techniques to accelerate noise modeling, transient prediction, Sim-to-Si analysis, or automated correlation checks, with sound judgment on model limitations.
• Demonstrated ability to drive cross-functional specifications to decision and sign-off.

Nice-to-have:

• Patents, publications, or reusable methodologies in power integrity/PDN/di/dt that demonstrate technical craft.
• Experience with GPU, CPU, or AI accelerator silicon at advanced nodes and multi-rail, multi-domain PDN ownership at SoC level.
• Track record of applying ML/AI to noise modeling or feature optimization with validation against measurements.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.