Senior Physical Design Verification Layout Engineer
NVIDIAJob Title
Senior Physical Design Verification Layout Engineer
Role Summary
NVIDIA is seeking experienced Physical Design Engineers to join its Networking Silicon engineering team. The team is responsible for developing high-speed communication devices with an emphasis on throughput and low latency.
Experience Level
Senior-level, with at least 5 years of hands-on layout experience.
Responsibilities
The engineer will be tasked with the following key responsibilities:
- Chip floorplan and pin placement integration.
- Running, debugging, and approving Physical Verification flows across multiple projects.
- Performing physical layout implementation, planning, and optimization.
Requirements
Ideal candidates should meet the following requirements:
- Bachelor's or Master's degree in Electrical Engineering.
- Minimum of 5 years of hands-on layout experience.
- Strong background in Physical Verification methodology, including ERC, LVS, and DRC.
- In-depth knowledge of advanced silicon process technologies.
- Familiarity with EDA tools such as Synopsys and Cadence.
- Collaborative team player.
- Orientation towards AI tools or a strong desire to learn them.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering.
About the Company
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
