Verification Design Lead

Job Title

Verification Design Lead

Role Summary

The Verification Design Lead is responsible for providing technical leadership in verification and mentoring junior engineers within a diverse engineering team. The role focuses on collaborating with global teams to ensure high-quality verification solutions for ASIC and IP designs.

Experience Level

Senior level; requires at least 12 years of direct industry experience in digital design verification.

Responsibilities

Key responsibilities include:

• Providing technical leadership and mentoring junior engineers.
• Collaborating with cross-functional, global teams.
• Defining and implementing advanced verification plans and methodologies.
• Developing and maintaining UVM-based testbenches.
• Driving process improvements for verification efficiency.
• Automating verification flows using scripting and programming skills.

Requirements

Must-have qualifications include:

• BSEE or MSEE with at least 12+ years of direct industry experience in digital design verification.
• Expertise in System Verilog, Verilog, VHDL, UVM, and coverage-driven RTL verification.
• Proficiency in scripting and programming (Python, Perl, C/C++).
• Ability to define verification plans and architect testbenches.
• Experience with 200G SerDes verification is an asset.

Education Requirements

BSEE or MSEE is required for this position.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.