Senior Physical Design Engineer, STA

Job Title

Senior Physical Design Engineer, STA

Role Summary

The HIPD SAM team delivers end-to-end physical design and analog layout for Client, Server and ASIC Hard-IP portfolios and advanced testchips. This role performs static timing analysis and timing optimization for mixed-signal IPs and SoC partitions, working with architecture, clocking, logic and backend teams to meet performance, power, and functionality targets.

Position is based in Bangalore and eligible for the employer's hybrid work model.

Experience Level

Senior-level. Guidance: approximately 4+ years of relevant timing/physical design experience.

Responsibilities

Key technical responsibilities:

• Perform static timing analysis (STA) and optimize timing at the IP and partition levels.
• Generate and verify timing constraints and address timing violations across complex SoC designs.
• Conduct timing rollups and ensure timing budgets meet functionality, performance, and power goals.
• Develop and optimize clock networks in collaboration with clocking and backend teams.
• Define methodologies and timing models to improve physical design team efficiency.
• Establish PVT (process, voltage, temperature) conditions for timing analysis based on product requirements.
• Drive timing fixes, clock balance, and coordinate timing closure and timing reviews with cross-functional teams.

Requirements

Must-have technical skills and experience:

• Proficiency in static timing analysis, timing budgeting, and timing-constraint development.
• Experience with timing rollups, timing-model methodologies, and setting analysis corners (PVT).
• Experience optimizing and verifying clock networks and clocking strategies.
• Proven ability to diagnose and resolve timing violations in complex designs.
• Experience collaborating with architecture, clocking, logic design, and backend teams on flow development and integration.
• Nice-to-have: experience with full-chip closure reviews, advanced low-power/performance optimizations, and methodology development.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related technical field. The posting specifies experience guidance of 4+ years with a Bachelor's degree or 3+ years with a Master's degree in timing analysis and optimization for SoC designs.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.