Senior Physical Design Engineer - Server SoC & Chiplet Implementation

Job Title

Senior Physical Design Engineer - Server SoC & Chiplet Implementation

Role Summary

Plan, build, and execute physical design for complex server SoC chiplets on advanced process nodes. Work on block-level and top-level implementation from concept through tape-out, collaborating with RTL/logic, verification, and system teams to deliver high-performance, low-power designs.

Experience Level

Senior — 8–12 years of experience in physical design and methodology on advanced nodes (examples: 5nm, 3nm).

Responsibilities

Primary technical and cross-functional responsibilities for the role.

• Plan and execute block-level and top-level physical implementation for chiplets in server SoC designs.
• Drive design of large blocks from initial concept through tape-out.
• Perform synthesis for high-speed designs and lead place-and-route flow execution and optimization.
• Analyze implementation results, troubleshoot timing, congestion, and physical issues, and apply optimizations.
• Integrate closely with RTL/logic designers and cross-functional teams to resolve design and integration issues.
• Apply low-power implementation techniques and validate power/state interactions with design constraints.
• Develop and use scripts and automation in a Unix/Linux environment to support flows and debug.
• Mentor peers and contribute to methodology improvements and design-for-manufacturability practices.

Requirements

Clear distinction between must-have skills and preferred strengths.

Must-have:

• Proven hands-on experience with block-level and top-level physical implementation on advanced nodes (5nm or below).
• Demonstrated ability to execute synthesis and lead place-and-route flows, including timing closure and optimization.
• Strong Unix/Linux proficiency and scripting skills (Tcl, Perl, sed/awk); solid debug capability.
• Experience with STA, physical verification concepts, and interpretation of implementation metrics.
• Strong problem-solving, communication, and teamwork skills in cross-functional projects.

Nice-to-have:

• Experience with multi-voltage / low-power implementation flows (UPF concepts, power-gating, isolation, level-shifters, voltage domains, power-state tables).
• Hands-on use of industry place & route tools such as Synopsys Fusion Compiler, ICC2, or Cadence Innovus.
• Familiarity with Python for flow automation and advanced scripting.
• Prior contribution to methodology development or large-scale tape-out projects.

Education Requirements

Master's or Bachelor's degree in Electronics Engineering.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.