Senior Physical Design Engineer - Neuromorphic Computing
Intel CorporationJob Title
Senior Physical Design Engineer - Neuromorphic Computing
Role Summary
Senior physical design engineer on Intel's neuromorphic silicon team responsible for physical integration across die and package, including chiplet and advanced packaging solutions. The role drives block- and chip-level closure to meet performance, power, and area targets.
This is a hands-on engineering position requiring physical design expertise, scripting to automate flows, and collaboration with RTL, verification, and packaging teams.
Experience Level
Senior — the posting specifies experienced hire level with multi-year hands-on physical design experience (see Education Requirements for the required experience equivalencies).
Responsibilities
Key responsibilities include end-to-end physical design and closure activities across die and package.
- Derive package and die-level requirements from system specifications.
- Architect full-chip floorplans and define partition-level floorplans with macro/pin placements and keep-outs.
- Collaborate with RTL designers to define timing constraints; run synthesis and place-and-route trials; fix timing, EM/IR, LVS and DRC issues.
- Run back-annotated simulations (VCS+SDF) and iterate to meet power/performance targets.
- Develop custom scripts and tool flows to manipulate synthesis and physical design tools for low-power/high-performance designs.
Requirements
Must-have technical experience and skills (education requirements are listed separately below).
- Hands-on physical design experience delivering silicon tape-outs (years requirements moved to Education Requirements).
- Experience setting up floorplans, defining timing and power constraints, and iterating through synthesis/place-and-route to meet KPIs.
- Proficiency with scripting languages such as Perl, TCL, Python for automation.
- Experience debugging FEV and RV reports and planning ECOs.
- Experience with chiplet integration and/or advanced packaging.
- Experience applying AI tools to set up tool flows, debug, or improve productivity.
Nice-to-have:
- Static timing experience with multiple interfaces (e.g., SerDes, UCIe).
- Experience with Cadence (Virtuoso) and Synopsys (Fusion Compiler, PrimeTime, StarRC, SiliconSmart, VCS) toolchains.
- EDA/CAD software development experience in object-oriented languages (Java, C++).
- Experience with asynchronous architectures and circuits.
Education Requirements
Minimum: Bachelor's degree plus 6+ years of hands-on physical design experience, or Master's degree plus 4+ years. The posting allows this experience to be obtained via a combination of degree, research, prior jobs, or internships (i.e., equivalent practical experience is acceptable). Specific fields of study are not specified in the posting.
About the Company
Company: Intel Corporation
Headquarters: Santa Clara, California, USA
Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.
