Senior Physical Design Engineer for Core IP

Job Title

Senior Physical Design Engineer for Core IP

Role Summary

Join the CPU development team to perform physical design for high-performance CPU core IP used across client, server, IoT and AI products. The role focuses on synthesis, place-and-route, timing and power convergence, and design closure on advanced process technologies.

Experience Level

Senior. The position expects senior-level experience (guidance in posting: typically 10+ years with a Bachelor's degree or 5+ years with a Master's degree).

Responsibilities

Primary responsibilities center on physical implementation and design convergence of CPU core blocks within a large SoC/IP context.

• Perform logic synthesis, place and route, static timing analysis, power analysis, and full design closure for high-speed CPU core blocks.
• Execute physical verification and signoff flows (FEV, DRC/LVS, electrical checks, noise and electromigration checks).
• Develop and refine synthesis and P&R flows, methodologies, and scripts to improve reproducibility and convergence.
• Root-cause timing and power issues and implement fixes across block and chip levels; collaborate with clocking and full-chip teams to balance timing, power, and partitioning.
• Document and communicate implementation plans, progress indicators, risks, and resource needs to stakeholders.

Requirements

Must-have technical experience and skills required for initial consideration are listed below. Preferred items are noted separately.

• Must-have: Significant hands-on experience in integrated circuit physical design and closure for CPU or large IP blocks (experience expectation indicated in posting).
• Experience with industry IC design tool flows (Synopsys or Cadence) covering logic synthesis, place & route, static timing analysis, and design closure.
• Proven experience achieving PV convergence, including static timing and power analysis.
• Experience with chip physical design verification: formal equivalence, timing and electrical checks, DRC/LVS, noise and electromigration checks.
• Scripting proficiency in TCL plus at least one other interpreted language (Perl, Python, Ruby, etc.).
• Demonstrated success synthesizing a digital logic block that was integrated into a large SoC or IP.
• Preferred / Nice-to-have: Floorplanning, routing and clock distribution best practices; RTL-to-GDS methodologies; Synopsys (Fusion Compiler, ICC2, PrimeTime) or Cadence (Genus/Innovus) expertise.
• CPU-level timing analysis and optimization experience; experience coordinating timing fixes with clocking and full-chip designers.

Education Requirements

Bachelor's degree in Computer Engineering, Electrical Engineering or a related field (posting guides to 10+ years' relevant experience) OR a Master's degree in the same fields (posting guides to 5+ years' relevant experience). No other certifications or degree requirements specified.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.