Senior Physical Design Engineer

Job Title

Senior Physical Design Engineer

Role Summary

Join Microsofts Compute Silicon & Manufacturing Engineering (CSME) within SCHIE to implement and sign off large SoC blocks for cloud infrastructure chips. The role focuses on physical design execution, clock construction, timing closure, and cross-functional coordination to deliver production silicon.

This position is an individual contributor role on a hardware engineering team; the worksite is hybrid (3 days/week in-office in Hillsboro, OR).

Experience Level

Senior. Typical candidates have 7+ years of semiconductor design experience; alternate experience combinations are detailed in Education Requirements.

Responsibilities

Primary responsibilities include hands-on physical design execution, signoff, and collaboration across design and tooling teams.

• Drive end-to-end implementation from synthesis through place-and-route and complete all signoff stages (timing, physical verification, EMIR, formal equivalence, low-power verification).
• Lead SOC clock construction and high-speed clock tree synthesis (CTS) strategies.
• Perform RTL-to-GDS implementation for SoC partitions and optimize blocks for manufacturability and performance.
• Explore and improve PD methodology and flows to optimize design quality, PPA, and cycle time.
• Coordinate with CAD/PD flow, RTL/design, DFT, architecture, power & performance, technology, and external partners.
• Communicate project status, risks, and plans clearly to stakeholders.
• Foster cross-team collaboration and apply a data-driven approach to influence tools, flows, and methodologies.

Requirements

Must-have screening and technical expectations; preferred skills listed separately.

• Ability to pass Microsoft Cloud Background Check and periodic security screenings required by Microsoft and customers.
• Must satisfy export-control eligibility; successful hire must verify citizenship or lawful residency (passport or other acceptable documentation) for access to export-controlled information.
• Proven technical expertise in physical design flows including synthesis, floorplanning, place-and-route, extraction, timing closure, and physical verification.
• Experience with clock construction strategies and CTS for high-speed designs.
• Strong communication, collaboration, and cross-functional teamwork skills.

Nice-to-have:

• Production silicon tape-outs in advanced foundry nodes.
• Experience with low-power design methodology and PPA trade-offs for SoC/subsystem design.
• Hands-on ownership of medium to large SoC block PD execution and PD/CAD flow optimization experience.
• Data-analysis and problem-solving skills to drive methodology improvements.

Education Requirements

Doctorate (PhD) in Electrical Engineering, Computer Engineering, Computer Science, or related field with 1+ year technical engineering experience; OR Masters degree in those fields with 4+ years experience; OR Bachelors degree in those fields with 5+ years experience; OR equivalent practical experience. Preferred: BS/MS in Electrical or Computer Engineering or related degree. (Summarizes all degree, field-of-study, and equivalent-experience language from the posting.)

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.