Senior Physical Design Engineer, Annapurna Labs (AWS)

Job Title

Senior Physical Design Engineer, Annapurna Labs (AWS)

Role Summary

Member of the Cloud-Scale Machine Learning Acceleration team responsible for physical design and optimization of custom SoCs and server hardware used in AWS ML servers (for example, Inferentia and Trainium). The role focuses on physical implementation, design closure, IP integration, and methodology development for datacenter accelerator platforms.

Experience Level

Senior — typically requires 6+ years of ASIC physical design experience; the posting specifies senior-level qualifications and multi-year domain experience.

Responsibilities

Key responsibilities include ownership of block/subsystem physical implementation and close collaboration with RTL and architecture teams.

• Collaborate with RTL/logic designers to evaluate architectural feasibility and power-performance-area trade-offs.
• Drive IO/core subsystem and block implementation: synthesis, floor planning, bus/pin planning, place & route, and ECO.
• Design and validate power/clock distribution, perform congestion analysis, timing closure, and IR drop analysis.
• Execute physical verification, sign-off activities (timing, IR/EM, physical verification), and handoff to GDSII.
• Develop and improve physical design methodologies and automation flows.
• Evaluate and integrate third-party IP; define and enforce physical IP requirements.
• Collaborate across teams and contribute to mentorship of junior engineers.

Requirements

Technical must-haves and preferred skills.

Must-have

• 6+ years of ASIC physical design experience (RTL-to-GDSII) at advanced process nodes (examples: 7nm, 14/16nm, 20nm, 28nm).
• Hands-on experience with EDA tools (Cadence, Mentor, Synopsys, or equivalent) across synthesis, place & route, and sign-off flows.
• Proven expertise in timing closure, power/clock distribution, congestion analysis, IR drop analysis, physical verification, and ECO.
• Experience scripting with Python, Perl, Bash, or PowerShell for automation.
• Deep understanding of sign-off activities (timing, IR/EM, physical verification).

Nice-to-have

• Experience mentoring, leading, or managing junior engineers.
• Experience developing CAD/physical design flows and automation.
• 4+ years integrating IP and driving IP requirements in the physical domain.
• Knowledge of device physics, custom/semi-custom implementation techniques, and technologies such as DDR, PCIe, and fabrics.
• Experience extracting design parameters, QOR metrics, and analyzing trends.

Education Requirements

Bachelor's degree (BS) plus 8+ years of relevant experience, or Master's degree (MS) plus 6+ years, in Electrical Engineering, Computer Science, or a closely related technical field.

About the Company

Company: KGS

KGS is a government and commercial contracting firm that provides engineering, technical, and staffing solutions, often supporting aerospace, defense, and IT projects for federal and industry customers.