Senior Physical Design Engineer, Annapurna Labs

Job Title

Senior Physical Design Engineer, Annapurna Labs

Role Summary

Design and optimize ASIC physical implementations for Annapurna Labs custom SoCs used in AWS machine-learning servers (Inferentia, Trainium). Work on RTL-to-GDSII physical design, sign-off, and methodology development as part of the Cloud-Scale Machine Learning Acceleration team.

Experience Level

Senior — expects an experienced engineer. Typical background: 6+ years in ASIC physical design (RTL-to-GDSII) and proven sign-off experience.

Responsibilities

Deliver physical design of complex SoC blocks and contribute to methodology and tool flows.

• Collaborate with RTL/logic and architecture teams to assess architectural feasibility and PPA trade-offs.
• Drive block/IO/core physical implementation: synthesis, floorplanning, pin/bus planning, place & route, and ECOs.
• Perform congestion, timing closure, IR drop analysis, power/clock distribution, and physical verification through sign-off.
• Develop and improve physical design methodologies and automated flows.
• Evaluate and integrate 3rd-party IP and define physical-domain IP requirements.
• Work collaboratively in a fast-paced, cross-functional team and support delivery at datacenter scale.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 6+ years of ASIC physical design experience (RTL-to-GDSII) with block-level design using EDA tools (examples: Cadence, Mentor Graphics, Synopsys).
• Hands-on experience across synthesis, equivalency verification, floorplanning, pin/bus planning, place & route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO.
• Strong scripting skills (Python, Perl, Bash, or PowerShell) for automation and flow development.
• Deep understanding of sign-off activities (timing, IR/EM, physical verification) and quality-for-release metrics.
• Ability to analyze QOR metrics and extract design parameters to drive improvements.

Nice-to-have:

• Experience mentoring or leading junior engineers.
• Experience integrating IP (4+ years) and specifying IP requirements for the physical domain.
• Knowledge of device physics, custom/semi-custom implementation techniques, and interfaces such as DDR, PCIe, and fabric interconnects.

Education Requirements

BS in Electrical Engineering or Computer Science plus 8+ years relevant experience, or MS in EE/CS plus 6+ years relevant experience (as stated in the posting).

About the Company

Company: KGS

KGS is a government and commercial contracting firm that provides engineering, technical, and staffing solutions, often supporting aerospace, defense, and IT projects for federal and industry customers.