Senior Physical Design Engineer
The Senior Physical Design Engineer is an individual contributor responsible for block-level physical implementation of Hard-IP and testchip designs within established methodologies. The role delivers RTL/netlist-to-GDSII execution, collaborates with cross-functional teams, and maintains execution rigor and quality gates.
Senior level. Typical experience: approximately 5–8 years in physical design (expectation varies by degree—see Education Requirements).
Execute block-level physical design tasks and drive closure to sign-off.
Must-have technical skills and attributes.
Nice-to-have: prior work on hard-IP or testchip projects, familiarity with STA workflows, or additional physical sign-off experience.
BS degree with ~6–8 years of relevant physical design experience, or MS degree with ~5–7 years of relevant physical design experience. Candidates with equivalent practical experience, internships, or relevant coursework in Electrical/Computer Engineering, Computer Science, VLSI, or related technical fields are also considered.
Company: Intel Corporation
Headquarters: Santa Clara, California, USA
Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.
