Senior Physical Design Engineer

Job Title

Senior Physical Design Engineer

Role Summary

Join the Data Center & Energy (DCE) physical design team to own and execute physical implementation of complex mixed-signal SoCs from floorplanning through GDSII signoff. The role covers mature analog processes and advanced deep-submicron digital nodes and requires close collaboration with RTL designers, analog layout engineers, verification, and lab teams to meet performance, power, and area targets.

Locations: Limerick, Ireland or Edinburgh, Scotland. Required travel: ~10%.

Experience Level

Senior-level. Typical guideline: 4+ years of ASIC/SoC physical design and implementation experience.

Responsibilities

Primary responsibilities include:

• Drive physical implementation from RTL handoff through signoff: floorplanning, power planning, placement, CTS, routing, and timing closure.
• Perform and close static timing analysis across PVT corners; resolve timing violations with design and layout teams.
• Develop and maintain power delivery networks; perform IR-drop and electromigration analysis and drive fixes to closure.
• Execute physical verification (DRC, LVS, antenna, ERC) and resolve issues to achieve clean signoff.
• Collaborate with analog layout engineers on mixed-signal integration, floorplan co-optimization, and constraint definition for analog/digital boundaries.
• Support DFT insertion, scan chain stitching, and ATPG pattern generation.
• Contribute to flow development, methodology improvements, and automation using scripting.
• Support silicon bring-up and debug; correlate physical design decisions with lab measurements.

Requirements

Must-have technical skills and experience; preferred items noted below.

• Must-have: 4+ years experience in ASIC/SoC physical design and implementation.
• Must-have: Proficiency with Cadence implementation and signoff tools (e.g., Genus, Innovus, Tempus, Conformal, Voltus, Pegasus).
• Must-have: Solid understanding of static timing analysis, CDC, and multi‑corner multi‑mode signoff practices.
• Must-have: Experience with both mature analog process nodes (e.g., 180nm BCD) and advanced digital/FinFET nodes.
• Must-have: Experience with power analysis (IR-drop, EM) and power intent (UPF/CPF).
• Must-have: Working knowledge of DFT methodologies (scan insertion, compression, ATPG, JTAG/boundary scan).
• Must-have: Scripting skills for automation and flow development (Tcl, Python, shell).
• Nice-to-have: Experience with mixed-signal SoC co-integration, advanced node physical design, multi-die/SiP, low-power techniques, and formal equivalence checking.
• Strong problem-solving, organization, and written/verbal communication skills; ability to work independently.

Education Requirements

Minimum: BS in Electrical or Computer Engineering (or equivalent practical experience). Preferred: MS in Electrical or Computer Engineering or related field. The posting explicitly allows equivalent experience in lieu of degree.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.