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Senior Physical Design Engineer

NVIDIA
October 2, 2026
Full-time
On-site
Santa Clara, California, United States
$168,000 - $310,500 USD yearly
Physical Design Jobs, Level - Senior

Job Title

Senior Physical Design Engineer

Role Summary

Responsible for end-to-end physical design and implementation of GPUs and other ASICs for desktop, laptop, workstation, and mobile markets. Work as part of a physical design team to define methodologies, flows, and chip-level implementation choices.

Expected to contribute to floorplanning, power and clock distribution, place & route, timing closure, and back-end verification. Applications will be accepted through October 3, 2026.

Experience Level

Senior - typically 8+ years of relevant VLSI physical design experience (the posting specifies 8+ years).

Responsibilities

The role includes ownership of physical design tasks across the full backend implementation flow. Key responsibilities:

  • Lead physical design and implementation for complex GPU/ASIC projects targeting advanced process nodes.
  • Establish and improve physical design methodologies and automation flows.
  • Develop chip floorplans and oversee power/clock distribution network design.
  • Perform place & route, timing closure, and back-end verification activities.
  • Prepare designs for static timing analysis, power and noise analysis, and IR drop analysis.
  • Collaborate across teams to ensure production-ready tapeouts and delivery to manufacturing.

Requirements

Must-have technical skills and experience; concise list of core qualifications follows.

  • 8+ years of experience in large-scale VLSI physical design implementation on advanced nodes (3nm–5nm).
  • Proven track record of delivering silicon to production.
  • Extensive hands-on experience with P&R, timing analysis, physical verification, and IR drop analysis using industry CAD tools (examples: Synopsys ICC2/DC/PT/STAR-RC/ICV; Cadence Innovus/Tempus/SeaHawk; Mentor tools).
  • Deep understanding of custom macro blocks (RAMs, CAMs, high-speed I/O drivers, PLLs) and correlation with extracted results.
  • Demonstrated experience in timing closure, clock and power distribution analysis, RC extraction and correlation, place/route, and tapeout flows.
  • Strong analytical and debugging skills for complex back-end issues.
  • Proficiency with scripting or automation tools such as Python, Perl, Tcl, and Make is helpful.
  • Experience with Power, Performance, and Area (PPA) improvement initiatives is a plus.

Education Requirements

Bachelor of Science in Electrical Engineering (BSEE) required or equivalent experience; Master of Science in Electrical Engineering (MSEE) preferred. The posting allows equivalent practical experience in lieu of formal degrees.


About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.

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Date Posted: 2026-10-02