Senior Physical Design Engineer

Job Title

Senior Physical Design Engineer

Role Summary

Join the VLSI Physical Design team to deliver physical implementation of complex SoC/IP blocks from netlist to GDSII. The role focuses on meeting timing, power, area, and reliability targets across advanced process nodes.

You will collaborate with RTL, synthesis, DFT, STA, package, and signoff teams, drive design quality, and improve PD methodologies and automation.

Experience Level

Senior — 8–10 years of relevant industry experience.

Responsibilities

Responsible for end-to-end physical implementation and signoff of digital blocks and subsystems.

• Own floorplanning, power planning, placement, CTS, routing, timing closure, and physical verification.
• Optimize designs for power, performance, and area (PPA).
• Execute timing closure across multiple operating modes and process corners.
• Analyze and resolve setup, hold, SI, IR-drop, electromigration (EM), and congestion issues.
• Support ECO implementation and tapeout activities.
• Develop and enhance PD methodologies, automation flows, and scripts to increase productivity.
• Review design quality, mentor junior engineers, and coordinate with global cross-functional teams.

Requirements

Must-have technical skills, tools experience, and methods required for the role. Education listed separately below.

• Strong hands-on expertise in floorplanning, power planning, placement optimization, CTS, routing, timing closure, and physical verification.
• Deep knowledge of static timing analysis (STA), multi-mode multi-corner (MMMC) methodologies, crosstalk and signal-integrity analysis, ECO flows, and timing signoff.
• Experience with physical signoff activities including IR-drop analysis, electromigration analysis, DRC/LVS closure, and reliability checks.
• Proven experience delivering designs at advanced process nodes and executing signoff methodologies.
• Practical experience with industry-standard EDA tools: Cadence Innovus, Synopsys ICC2, PrimeTime, Tempus, RedHawk/Voltus, StarRC/Quantus, and Calibre.
• Ability to debug complex PPA and SI issues, work across corners and modes, and implement ECOs for tapeout.
• Experience developing automation and scripting to improve PD flow efficiency; ability to mentor peers.
• Clear communication and collaboration skills for cross-functional project delivery.

Education Requirements

Bachelor's or Master's degree in Electronics, VLSI, Electrical Engineering, or a closely related technical field.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.