Senior Physical Design and Timing Engineer
NVIDIAJob Title
Senior Physical Design and Timing Engineer
Role Summary
The Senior Physical Design and Timing Engineer drives physical design and timing closure for high-frequency, low-power CPUs, GPUs, LPUs and SoCs. The role covers RTL-to-GDSII implementation, static timing analysis, timing and power convergence, ECO implementation, and collaboration with cross-functional teams and methodology groups to improve flows.
Experience Level
Senior. Typical guidance: 5+ years experience with a BS or 3+ years with an MS in relevant fields (see Education Requirements for details).
Responsibilities
Primary responsibilities include:
- Lead physical design and timing at block, cluster, and full-chip levels.
- Drive front-end and back-end implementation from RTL to GDSII: synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECOs.
- Perform and own full-chip/sub-chip static timing analysis, timing constraint generation, and timing convergence.
- Plan critical paths and develop timing strategies to meet frequency and power targets.
- Collaborate across teams and with the Methodology team to improve convergence flows and automation.
Requirements
Must-have skills and experience:
- Proven experience in full-chip/sub-chip static timing analysis, timing constraints management, and timing convergence.
- Hands-on experience in logic synthesis and equivalence checking / functional verification.
- Expertise in physical design optimization (placement, routing, cell sizing, buffering, logic restructuring) and implementing ECOs.
- Experience with DFT logic and design closure.
- Understanding of crosstalk, noise/glitch analysis, electrical/manufacturing rules in deep-submicron processes and variation-aware convergence.
- Proficiency with industry-standard EDA tools and scripting/programming (Perl, Tcl, Make, Python, or similar).
Nice-to-have:
- Background in high-performance CPU/GPU/LPU implementation and timing convergence.
- Experience with DFT timing closure for scan/capture, transition faults, BIST.
- Experience in methodology or flow development and automation.
Education Requirements
BS in Electrical or Computer Engineering (or equivalent practical experience) typically with 5+ years; or MS in Electrical or Computer Engineering (or equivalent practical experience) typically with 3+ years. The posting explicitly accepts equivalent experience in lieu of a degree.
About the Company
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
