Senior Performance Modeling Architect, CPU Fabric and LLC

Job Title

Senior Performance Modeling Architect, CPU Fabric and LLC

Role Summary

Lead the architectural definition and improvement of CPU cache hierarchies and coherent interconnects. Build and maintain high-fidelity, cycle-accurate performance models that drive data-movement decisions across silicon for automotive and data-center products.

Work as a core member of the architecture team to analyze performance bottlenecks at multiple scales, validate models against silicon, and collaborate with verification and software teams to optimize system-level behavior.

Experience Level

Senior-level. Requires 5+ years of relevant industry experience.

Responsibilities

Primary responsibilities include developing detailed performance models, running benchmark-driven analyses, and collaborating across hardware and software teams.

• Develop and maintain cycle-accurate performance models (C++/SystemC) for coherent interconnects and large shared caches.
• Model and analyze performance bottlenecks across scales from automotive SoCs to large multi-mesh data-center architectures.
• Evaluate performance impact of coherency protocols and snooping filters.
• Run and analyze industry-standard benchmarks (SPEC, MLPerf, automotive suites) to inform architectural trade-offs.
• Correlate performance models with silicon measurements and work with software teams to optimize drivers and topology-aware code.

Requirements

Must-have technical skills and experience.

• Deep understanding of CPU microarchitecture, memory consistency models, and cache coherency protocols.
• Proven experience implementing performance models in C++ or SystemC.
• Proficiency in Python or similar scripting languages for data processing, visualization, and automation.
• Familiarity with Network-on-Chip topologies (Mesh, Ring, Torus), credit-based flow control, and arbitration logic.

Nice-to-have:

• Practical experience addressing ISO 26262 functional-safety requirements in automotive chips and PPA trade-offs for data-center designs.
• Experience defining or using PMU (performance monitoring unit) events on silicon or emulators.
• Background in formal methods or mathematical modeling for coherency state machines.
• Experience building internal tooling or frameworks for architectural exploration.
• Knowledge of emerging memory technologies such as CXL or HBM.

Education Requirements

Master's or Ph.D. in Computer Engineering, Electrical Engineering, or Computer Science with a focus on architecture, or equivalent practical experience.

Benefits information: https://www.nvidia.com/en-us/benefits/

Applications for this job will be accepted at least until May 10, 2026.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.