Senior PD Engineer: Synthesis & STA

Job Title

Senior PD Engineer: Synthesis & STA

Role Summary

VLSI Synthesis & STA specialist responsible for end-to-end ownership of logic synthesis and quality signoff for designated blocks and sub-chips. Acts as a bridge between RTL designers and physical implementation teams to deliver synthesis-ready netlists that meet performance, area, and power targets.

Role includes advising on RTL structure to optimize netlists and a growth path into adjacent physical design areas such as Place & Route and full-chip timing convergence.

Experience Level

Senior — typically 5 to 8 years of ASIC/SoC logic synthesis and static timing analysis experience.

Responsibilities

Key responsibilities include driving synthesis execution, ensuring timing signoff quality, and providing RTL guidance to meet aggressive frequency targets.

• Lead logic synthesis for assigned blocks and sub-chips to meet area, power, and performance targets.
• Define, execute, and monitor synthesis signoff checks to ensure netlist quality.
• Collaborate with RTL engineers to deliver clean, fully linted netlists prior to handoff.
• Analyze timing paths to control Levels of Logic (LOL) and meet high-frequency requirements.
• Provide actionable RTL coding guidelines, structural recommendations, and micro-architecture inputs to reduce logic depth and timing violations.
• Progressively take on responsibilities in PNR execution, STA signoff, and full-chip timing convergence.

Requirements

Must-have technical skills and experience:

• 5–8 years of ASIC/SoC Logic Synthesis and Static Timing Analysis experience.
• Hands-on experience with synthesis tools; strong preference for Cadence Genus.
• Proficiency with STA signoff tools such as Synopsys PrimeTime or Cadence Tempus.
• Solid knowledge of STA concepts, SDC constraints, delay calculation, and multi-mode multi-corner (MMMC) analysis.
• Strong Verilog/SystemVerilog skills, digital logic design, and experience with RTL linting/CDC tools.
• Experience analyzing datapath architectures and recommending RTL changes to optimize netlists.
• Scripting proficiency in Tcl, Python, or Perl for flow automation and reporting.
• Strong analytical and cross-functional communication skills.

Nice-to-have:

• Exposure to PNR flows (e.g., Innovus, ICC2) and understanding of synthesis impact on placement/routing congestion.
• Experience with Formal Verification / Logic Equivalence Checking (LEC/Formality).
• Experience with advanced technology nodes (5nm, 3nm).

Education Requirements

Not specified.

About the Company

Company: EnCharge AI

EnCharge AI develops advanced AI hardware and software systems for edge-to-cloud computing, focusing on in-memory computing technology to deliver high compute efficiency and density with low power consumption. Founded in 2022, the company targets power-, energy-, and space-constrained applications with integrated hardware architectures and software stacks for scalable, reliable AI deployment.