Senior Packaging Development Engineer - Leadframe Package/Ceramic

Job Title

Senior Packaging Development Engineer - Leadframe Package/Ceramic

Role Summary

Lead development and qualification of leadframe, ceramic and multi-chip-module (MCM) power packaging processes with emphasis on manufacturability, reliability and cost. Work with cross-functional and global teams to define process flows, characterize assemblies, and transfer designs to production.

Primary responsibilities include process optimization, product prototyping and qualification, failure-mode analysis, and enabling package competitiveness for power-stage applications.

Experience Level

Senior-level. Minimum 5 years of experience in semiconductor manufacturing (assembly/packaging/SMT) as stated in the posting.

Responsibilities

Key duties include:

• Develop and optimize front-of-line (FOL) and end-of-line (EOL) processes such as Face-to-Face flip chip, reflow, swivel molding for dual-side cooling MCM packages.
• Define simplified manufacturing process sequences for power-stage packages and ensure Design for Manufacturability.
• Manage new product executions from kick-off through prototyping, characterization, learning cycles, and qualification to product release using engineering methods (JMP analysis, FMEA, control plans).
• Collaborate with factory operations to meet manufacturing indices, quality standards, and cost targets.
• Engage with global package-platform and emerging-technology teams to execute technology roadmaps and establish process capabilities.
• Enable MCM/package competitiveness by adopting industry capabilities and maximizing design flexibility.
• Coordinate with cross-functional teams to perform stress and reliability modeling and define mitigation or contingency plans.

Requirements

Must-have and preferred technical qualifications.

Must-have:

• Minimum 5 years of experience in the semiconductor manufacturing/assembly field.
• Expert-level experience in process development for power-stage packages and multi-chip modules.
• Package layer design expertise: structural configuration, material selection, and process-flow design.
• Hands-on skills operating assembly equipment, down-selecting materials, process optimization and yield improvement.
• Expert experience using ANSYS/FEA for stress and mechanical modeling.

Nice-to-have:

• Experience with system-in-package (SiP), package-on-package, or multi-chip package assemblies.
• Understanding of DFM constraints, defect criteria, and integration between SMT and back-end packaging processes.
• Familiarity with FMEA, control plans, SPC, DOE methodologies and JMP statistical software.
• Project management experience in assembly/test or SMT operations and experience working with suppliers and global teams.
• Knowledge of leadframe, DBC, MIS manufacturing and power module substrate design and reliability requirements.

Education Requirements

Bachelor's degree required in Mechanical Engineering, Physics, Materials Science, or a related field. Posting specifies cumulative GPA > 3.3. No substitute-equivalence language provided in the source.

About the Company

Company: Texas Instruments

Headquarters: Dallas, Texas, USA

Texas Instruments is a global semiconductor company that designs, manufactures, and sells analog and embedded processing chips for various markets including industrial, automotive, and personal electronics. The company's innovations aim to make electronics more affordable and reliable, fostering advancements in technology through each generation of semiconductors.