Senior Mixed-Signal Verification Engineer

Job Title

Senior Mixed-Signal Verification Engineer (Sr./Staff)

Role Summary

Lead mixed-signal design and verification for complex ASICs in power-management and mixed-signal product lines. The role supervises multiple projects, develops verification environments and behavioral models, and supports post-silicon validation.

The position involves mentoring and recruiting for the mixed-signal design team and close collaboration with analog, layout, digital design, verification and physical-design engineers.

Experience Level

Senior-level (Sr. / Staff). See Education Requirements for specific years-of-experience guidance for Sr. and Staff levels.

Responsibilities

Primary responsibilities include leading verification activities, supporting silicon bring-up, and coordinating across design teams.

• Lead mixed-signal design verification, environment development, and validation for ASIC projects.
• Train, mentor and supervise mixed-signal designers; participate in recruitment.
• Define analog-digital interfaces and produce related documentation.
• Develop behavioral models for analog blocks and perform architectural trade-off analyses.
• Perform analog, digital and mixed-mode simulations and debug issues across domains.
• Support digital teams with timing, I/O and DFT constraints and mixed-signal timing considerations.
• Provide post-silicon validation and characterization support.
• Collaborate closely with analog design, layout, digital design, verification and physical implementation teams.

Requirements

Must-have technical skills and experience for effective performance in this role.

Must-have:

• Proven experience in transistor-level analog and mixed-signal circuit design and verification.
• Strong knowledge of full ASIC development flow and silicon fabrication process.
• Understanding of device mismatches, noise, linearity, stability and other analog effects.
• Experience with layout best practices and layout-awareness for design/verification.
• Experience with SPICE-level simulators (Spectre, HSPICE or equivalent) and complex simulations (Monte-Carlo, noise, stability).
• Proficiency with Cadence tools such as ADE-L and ADE-XL.
• Experience with DRC/LVS flows using Calibre, ICV, or equivalents.
• Experience with mixed-mode Verilog-AMS simulations; Verilog, SystemVerilog and Verilog-A for behavioral modeling.
• Knowledge of DFT techniques (SCAN, LBIST, ABIST, IDDQ) and STA/mixed-signal timing/IO constraints.
• Good leadership, communication skills, and ability to work independently and across teams.

Nice-to-have:

• Experience with automotive ASIL standards and automotive-quality processes.
• Background in power-management applications and protocols (I2C, I3C, SPI, USB, PMBUS).
• Familiarity with version control and design-data management tools (GitLab, Cliosoft SOS).

Education Requirements

For Staff level: BSEE + 12 years experience or MSEE + 8 years experience. For Sr. level: BSEE + 7 years experience or MSEE + 5 years experience in ASIC mixed-signal design.

About the Company

Company: Monolithic Power Systems

Headquarters: San Jose, California, USA

Monolithic Power Systems, Inc. (MPS) is a leading provider of energy-efficient power solutions for various applications, including industrial, telecom, automotive, and consumer sectors. Known for their cutting-edge integrated power semiconductors, MPS emphasizes innovation, sustainability, and creativity, making them one of the fastest-growing companies in the semiconductor industry.