Senior Mixed Signal DV Engineer

Job Title

Senior Mixed Signal DV Engineer

Role Summary

Design Verification engineer responsible for verification of analog and mixed-signal ICs from pre-layout through tape-out and post-silicon support. Work within the Advanced Circuits and Power Solutions organization, collaborating with architecture, design, firmware, process, packaging, and customer teams.

Primary mission: define and execute coverage-driven mixed-signal verification strategies, develop UVM-based environments and analog models, and drive sign-off for high-volume custom IC products.

Experience Level

Senior - minimum 12 years of relevant experience.

Responsibilities

Accountabilities include verification strategy, environment development, modeling, execution, and cross-functional technical leadership.

• Define verification strategy, test plans, test cases, checkers, and coverage metrics for mixed-signal designs.
• Architect and implement UVM-based verification environments (agents, drivers, monitors, scoreboards).
• Develop analog behavioral models (Verilog-A/Verilog-AMS/Wreal) and integrate schematics, models, and RTL into testbenches.
• Execute RTL and gate-level regressions, manage regressions, and drive functional and code coverage closure through tape-out.
• Implement analog checkers, assertions, and post-processing verification flows across domains.
• Troubleshoot complex verification and design issues; provide technical debug and root-cause analysis.
• Support post-silicon activities including ATE pattern generation and silicon characterization.
• Collaborate with internal and external stakeholders to drive design governance and industry best practices.

Requirements

Must-have skills and technologies required for immediate contribution; preferred items listed separately.

Must-have

• Strong SystemVerilog and UVM methodology experience.
• Experience with mixed-signal verification flows combining schematics, behavioral models, and RTL.
• Analog behavioral modeling using Verilog-AMS, Verilog-A, or Wreal (RNM).
• Proficiency with Cadence simulation/debug tools (e.g., Xcelium, vManager, JasperGold, Virtuoso, AMS Designer) or equivalent.
• Hands-on Formal Property Verification (FPV), connectivity checks, and UNR analysis for top-level sign-off.
• Experience writing and debugging CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) assertions.
• Practical experience with UPF and power-aware verification methodologies.
• Strong verbal and written communication skills for cross-functional collaboration and customer interaction.

Nice-to-have

• Scripting and automation using Python, Perl, or Shell to automate verification flows and data analysis.
• Experience with AI/ML techniques applied to verification or coverage improvement.
• Domain experience in PMICs, signal processing, or high-speed communication interfaces.
• Hands-on verification of standard protocols (I2C, SPI, UART, ASI).
• Post-silicon debug and close collaboration with silicon validation teams.

Education Requirements

Master's or Bachelor's degree in Electrical Engineering (or equivalent). The posting explicitly allows equivalent practical experience in lieu of a degree.

About the Company

Company: Texas Instruments

Headquarters: Dallas, Texas, USA

Texas Instruments is a global semiconductor company that designs, manufactures, and sells analog and embedded processing chips for various markets including industrial, automotive, and personal electronics. The company's innovations aim to make electronics more affordable and reliable, fostering advancements in technology through each generation of semiconductors.